501 lines
14 KiB
C
501 lines
14 KiB
C
/****************************************************************************
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* drivers/coresight/coresight_etb.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <errno.h>
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#include <debug.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include <nuttx/bits.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/fs/fs.h>
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#include <nuttx/coresight/coresight_etb.h>
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#include "coresight_common.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ETB registers */
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#define ETB_RAM_DEPTH_REG 0x004
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#define ETB_STATUS_REG 0x00c
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#define ETB_RAM_READ_DATA_REG 0x010
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#define ETB_RAM_READ_POINTER 0x014
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#define ETB_RAM_WRITE_POINTER 0x018
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#define ETB_TRG 0x01c
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#define ETB_CTL_REG 0x020
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#define ETB_RWD_REG 0x024
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#define ETB_FFSR 0x300
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#define ETB_FFCR 0x304
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#define ETB_ITMISCOP0 0xee0
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#define ETB_ITTRFLINACK 0xee4
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#define ETB_ITTRFLIN 0xee8
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#define ETB_ITATBDATA0 0xeeC
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#define ETB_ITATBCTR2 0xef0
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#define ETB_ITATBCTR1 0xef4
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#define ETB_ITATBCTR0 0xef8
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/* STS - 0x00C */
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#define ETB_STATUS_RAM_FULL BIT(0)
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/* CTL - 0x020 */
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#define ETB_CTL_CAPT_EN BIT(0)
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/* FFCR - 0x304 */
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#define ETB_FFCR_EN_FTC BIT(0)
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#define ETB_FFCR_FON_MAN BIT(6)
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#define ETB_FFCR_STOP_FI BIT(12)
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#define ETB_FFCR_STOP_TRIGGER BIT(13)
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#define ETB_FFSR_FT_STOPPED BIT(1)
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#define ETB_FRAME_SIZE_WORDS 4
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#define ETB_MAX_NAME_LEN 32
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/****************************************************************************
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* Private Functions Prototypes
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****************************************************************************/
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static int etb_enable(FAR struct coresight_dev_s *csdev);
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static void etb_disable(FAR struct coresight_dev_s *csdev);
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static int etb_open(FAR struct file *filep);
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static int etb_close(FAR struct file *filep);
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static ssize_t etb_read(FAR struct file *filep, FAR char *buffer,
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size_t buflen);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const struct coresight_sink_ops_s g_etb_sink_ops =
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{
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.enable = etb_enable,
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.disable = etb_disable,
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};
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static const struct coresight_ops_s g_etb_ops =
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{
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.sink_ops = &g_etb_sink_ops,
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};
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static const struct file_operations g_etb_fops =
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{
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etb_open, /* open */
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etb_close, /* close */
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etb_read, /* read */
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NULL, /* write */
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NULL, /* seek */
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NULL, /* ioctl */
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: etb_hw_enable
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****************************************************************************/
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static void etb_hw_enable(FAR struct coresight_etb_dev_s *etbdev)
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{
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uint32_t i;
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coresight_unlock(etbdev->csdev.addr);
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/* Clear entire RAM buffer. */
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coresight_put32(0x0, etbdev->csdev.addr + ETB_RAM_WRITE_POINTER);
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for (i = 0; i < etbdev->buffer_depth; i++)
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{
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coresight_put32(0x0, etbdev->csdev.addr + ETB_RWD_REG);
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}
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/* Reset read/write RAM pointer. */
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coresight_put32(0x0, etbdev->csdev.addr + ETB_RAM_WRITE_POINTER);
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coresight_put32(0x0, etbdev->csdev.addr + ETB_RAM_READ_POINTER);
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/* Set trigger event. */
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coresight_put32(etbdev->trigger_cntr, etbdev->csdev.addr + ETB_TRG);
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coresight_put32(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
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etbdev->csdev.addr + ETB_FFCR);
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/* Enable trace capture. */
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coresight_put32(ETB_CTL_CAPT_EN, etbdev->csdev.addr + ETB_CTL_REG);
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coresight_lock(etbdev->csdev.addr);
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}
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/****************************************************************************
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* Name: etb_hw_read
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*
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* Description:
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* Dump ETB RAM buffer to device's buffer for usrspace's read.
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*
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* Input Parameters:
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* etbdev - Pointer to the ETB device.
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*
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****************************************************************************/
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static void etb_hw_read(FAR struct coresight_etb_dev_s *etbdev)
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{
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uint32_t readptr;
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uint32_t writeptr;
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uint32_t frameoff;
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FAR uint32_t *bufptr;
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bool lost = false;
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uint32_t i;
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coresight_unlock(etbdev->csdev.addr);
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/* ARM recommends that addresses are 128-bit aligned. Read from 0 when ETB
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* buffer is not full, otherwise, read from writepointer and there are some
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* trace data has been overwriten and lost.
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*/
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readptr = coresight_get32(etbdev->csdev.addr + ETB_RAM_READ_POINTER);
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writeptr = coresight_get32(etbdev->csdev.addr + ETB_RAM_WRITE_POINTER);
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frameoff = writeptr % ETB_FRAME_SIZE_WORDS;
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if (frameoff != 0)
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{
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cserr("writeptr: 0x%" PRIx32 " not aligned to formatter frame size\n",
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writeptr);
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writeptr += ETB_FRAME_SIZE_WORDS - frameoff;
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}
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if ((coresight_get32(etbdev->csdev.addr + ETB_STATUS_REG) &
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ETB_STATUS_RAM_FULL) == 0)
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{
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coresight_put32(0x0, etbdev->csdev.addr + ETB_RAM_READ_POINTER);
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}
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else
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{
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coresight_put32(writeptr, etbdev->csdev.addr + ETB_RAM_READ_POINTER);
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lost = true;
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}
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bufptr = etbdev->bufptr;
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for (i = 0; i < etbdev->buffer_depth; i++)
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{
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*bufptr = coresight_get32(etbdev->csdev.addr + ETB_RAM_READ_DATA_REG);
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bufptr += 1;
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}
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if (lost == true)
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{
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coresight_insert_barrier_packet(etbdev->bufptr);
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}
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/* Clear content between frameoff and ETB_FRAME_SIZE_WORDS - frameoff. */
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if (frameoff)
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{
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bufptr -= ETB_FRAME_SIZE_WORDS - frameoff;
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for (i = 0; i < ETB_FRAME_SIZE_WORDS - frameoff; i++)
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{
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*bufptr = 0x0;
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bufptr += 1;
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}
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}
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coresight_put32(readptr, etbdev->csdev.addr + ETB_RAM_READ_POINTER);
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coresight_lock(etbdev->csdev.addr);
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}
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/****************************************************************************
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* Name: etb_hw_disable
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****************************************************************************/
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static void etb_hw_disable(FAR struct coresight_etb_dev_s *etbdev)
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{
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coresight_unlock(etbdev->csdev.addr);
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/* Trigger a formatter stop event. */
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coresight_modify32(ETB_FFCR_STOP_FI, ETB_FFCR_STOP_FI,
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etbdev->csdev.addr + ETB_FFCR);
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coresight_modify32(ETB_FFCR_FON_MAN, ETB_FFCR_FON_MAN,
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etbdev->csdev.addr + ETB_FFCR);
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if (coresight_timeout(0x0, ETB_FFCR_FON_MAN,
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etbdev->csdev.addr + ETB_FFCR) < 0)
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{
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cserr("timeout while waiting for completion of Manual Flush\n");
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}
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/* Disable trace capture. */
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coresight_put32(0x0, etbdev->csdev.addr + ETB_CTL_REG);
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if (coresight_timeout(ETB_FFSR_FT_STOPPED, ETB_FFSR_FT_STOPPED,
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etbdev->csdev.addr + ETB_FFSR) < 0)
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{
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cserr("timeout while waiting for Formatter to Stop\n");
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}
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coresight_lock(etbdev->csdev.addr);
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}
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/****************************************************************************
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* Name: etb_enable
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****************************************************************************/
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static int etb_enable(FAR struct coresight_dev_s *csdev)
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{
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FAR struct coresight_etb_dev_s *etbdev =
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(FAR struct coresight_etb_dev_s *)csdev;
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int ret;
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ret = coresight_claim_device(etbdev->csdev.addr);
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if (ret < 0)
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{
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return ret;
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}
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etb_hw_enable(etbdev);
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return ret;
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}
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/****************************************************************************
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* Name: etb_disable
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****************************************************************************/
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static void etb_disable(FAR struct coresight_dev_s *csdev)
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{
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FAR struct coresight_etb_dev_s *etbdev =
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(FAR struct coresight_etb_dev_s *)csdev;
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etb_hw_disable(etbdev);
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coresight_disclaim_device(etbdev->csdev.addr);
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}
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/****************************************************************************
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* Name: etb_open
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****************************************************************************/
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static int etb_open(FAR struct file *filep)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct coresight_etb_dev_s *etbdev;
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int ret;
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DEBUGASSERT(inode->i_private);
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etbdev = (FAR struct coresight_etb_dev_s *)inode->i_private;
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ret = nxmutex_lock(&etbdev->lock);
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if (ret < 0)
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{
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return ret;
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}
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if (etbdev->opencnt++ == 0)
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{
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/* Each buffer line is 32bit size. */
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etbdev->bufptr = kmm_zalloc(etbdev->buffer_depth * 4);
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if (etbdev->bufptr == NULL)
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{
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cserr("malloc buffer failed\n");
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etbdev->opencnt--;
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ret = -ENOMEM;
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}
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else
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{
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irqstate_t flags;
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flags = enter_critical_section();
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if (etbdev->csdev.refcnt > 0)
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{
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etb_hw_disable(etbdev);
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}
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etb_hw_read(etbdev);
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if (etbdev->csdev.refcnt > 0)
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{
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etb_hw_enable(etbdev);
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}
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leave_critical_section(flags);
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}
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}
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nxmutex_unlock(&etbdev->lock);
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return ret;
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}
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/****************************************************************************
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* Name: etb_close
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****************************************************************************/
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static int etb_close(FAR struct file *filep)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct coresight_etb_dev_s *etbdev;
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int ret;
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DEBUGASSERT(inode->i_private);
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etbdev = (FAR struct coresight_etb_dev_s *)inode->i_private;
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ret = nxmutex_lock(&etbdev->lock);
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if (ret < 0)
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{
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return ret;
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}
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if (--etbdev->opencnt == 0)
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{
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kmm_free(etbdev->bufptr);
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}
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nxmutex_unlock(&etbdev->lock);
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return ret;
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}
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/****************************************************************************
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* Name: etb_read
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****************************************************************************/
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static ssize_t etb_read(FAR struct file *filep, FAR char *buffer,
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size_t buflen)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct coresight_etb_dev_s *etbdev;
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DEBUGASSERT(inode->i_private);
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etbdev = (FAR struct coresight_etb_dev_s *)inode->i_private;
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if (filep->f_pos > etbdev->buffer_depth * 4)
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{
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return 0;
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}
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if (filep->f_pos + buflen > etbdev->buffer_depth * 4)
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{
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buflen = etbdev->buffer_depth * 4 - filep->f_pos;
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}
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memcpy(buffer, (char *)etbdev->bufptr + filep->f_pos, buflen);
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filep->f_pos += buflen;
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return buflen;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: etb_register
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*
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* Description:
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* Register an etb devices.
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*
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* Input Parameters:
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* desc - A description of this coresight device.
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*
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* Returned Value:
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* Pointer to an etb device on success; NULL on failure.
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*
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****************************************************************************/
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FAR struct coresight_etb_dev_s *
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etb_register(FAR const struct coresight_desc_s *desc)
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{
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FAR struct coresight_etb_dev_s *etbdev;
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FAR struct coresight_dev_s *csdev;
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char pathname[ETB_MAX_NAME_LEN];
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int ret;
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etbdev = kmm_zalloc(sizeof(struct coresight_etb_dev_s));
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if (etbdev == NULL)
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{
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cserr("%s:malloc failed!\n", desc->name);
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return NULL;
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}
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coresight_unlock(desc->addr);
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etbdev->buffer_depth = coresight_get32(desc->addr + ETB_RAM_DEPTH_REG);
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coresight_lock(desc->addr);
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if (etbdev->buffer_depth & 0x80000000)
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{
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cserr("%s:etb buffer depth is invalid\n", desc->name);
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goto buf_err;
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}
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csdev = &etbdev->csdev;
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csdev->ops = &g_etb_ops;
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ret = coresight_register(csdev, desc);
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if (ret < 0)
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{
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cserr("%s:coresight register failed\n", desc->name);
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goto buf_err;
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}
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snprintf(pathname, sizeof(pathname), "/dev/%s", desc->name);
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ret = register_driver(pathname, &g_etb_fops, 0444, etbdev);
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if (ret < 0)
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{
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cserr("%s:driver register failed\n", desc->name);
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goto drv_err;
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}
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nxmutex_init(&etbdev->lock);
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return etbdev;
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drv_err:
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coresight_unregister(csdev);
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buf_err:
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kmm_free(etbdev);
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return NULL;
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}
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/****************************************************************************
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* Name: etb_unregister
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*
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* Description:
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* Unregister an etb devices.
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*
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* Input Parameters:
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* etbdev - Pointer to the etb device.
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*
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****************************************************************************/
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void etb_unregister(FAR struct coresight_etb_dev_s *etbdev)
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{
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char pathname[ETB_MAX_NAME_LEN];
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snprintf(pathname, sizeof(pathname), "/dev/%s", etbdev->csdev.name);
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unregister_driver(pathname);
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coresight_unregister(&etbdev->csdev);
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nxmutex_destroy(&etbdev->lock);
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kmm_free(etbdev);
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}
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