193 lines
5.5 KiB
Plaintext
193 lines
5.5 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_BOARD_ESP32CORE
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choice
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prompt "On-board Crystal Frequency"
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default ESP32CORE_XTAL_40MZ
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config ESP32CORE_XTAL_40MZ
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bool "40MHz"
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config ESP32CORE_XTAL_26MHz
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bool "26MHz"
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endchoice # On-board Crystal Frequency
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config ESP32CORE_RUN_IRAM
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bool "Run from IRAM"
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default n
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---help---
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The default configuration is set up run from IRAM. However, the
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current (2016-11-14) OpenOCD for ESP32 does not support writing to
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FLASH. This option sets up the linker scripts to support execution
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from IRAM. In this case, OpenOCD can be used to load directly into
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IRAM.
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At this stage the nuttx image is small enough to be entirely memory-
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resident. Once board support is more mature you can add flash cache
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mapping code to run from SPI flash after initial boot. There are at
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least two possible approaches you could take: You can add the flash
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cache mapping code into nuttx directly, so it is self-contained -
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early nuttx initialization runs from IRAM and enables flash cache,
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and then off you go. Or you can use the esp-idf software bootloader
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and partition table scheme and have nuttx be an esp-idf "app" which
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allows interoperability with the esp-idf system but makes you
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reliant on the esp-idf design for these parts. Both are possible.
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config ESP32CORE_FLASH_IMAGE
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bool "esp32 flash image"
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default n
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---help---
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Create flash_image.bin mainly used for QEMU.
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choice
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prompt "SPIFLASH File System"
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default ESP32_SPIFLASH_SMARTFS
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depends on ESP32_SPIFLASH
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config ESP32_SPIFLASH_SMARTFS
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bool "SmartFS"
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depends on FS_SMARTFS
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config ESP32_SPIFLASH_NXFFS
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bool "NXFFS"
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depends on FS_NXFFS
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config ESP32_SPIFLASH_SPIFFS
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bool "SPIFFS"
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depends on FS_SPIFFS
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config ESP32_SPIFLASH_LITTLEFS
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bool "LittleFS"
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depends on FS_LITTLEFS
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endchoice
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config ESP32_SPIFLASH_ENCRYPTION_TEST
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bool "SPI Flash encryption test"
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default n
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depends on ESP32_SPIFLASH
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select DEBUG_ASSERTIONS
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help
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Enable SPI Flash encryption test. This option will also select
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DEBUG_ASSERTIONS to enable kernel assert macro.
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config ESP32_SPIFLASH_TEST_ADDRESS
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hex "SPI Flash test address"
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default 0x180000
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depends on ESP32_SPIFLASH_ENCRYPTION_TEST
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help
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SPI Flash encryption test read/write address.
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if PM
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config PM_ALARM_SEC
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int "PM_STANDBY delay (seconds)"
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default 15
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depends on PM
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---help---
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Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
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config PM_ALARM_NSEC
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int "PM_STANDBY delay (nanoseconds)"
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default 0
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depends on PM
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---help---
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Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
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config PM_SLEEP_WAKEUP_SEC
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int "PM_SLEEP delay (seconds)"
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default 20
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depends on PM
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---help---
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Number of seconds to wait in PM_SLEEP.
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config PM_SLEEP_WAKEUP_NSEC
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int "PM_SLEEP delay (nanoseconds)"
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default 0
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depends on PM
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---help---
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Number of additional nanoseconds to wait in PM_SLEEP.
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endif # PM
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if ESP32_SPIRAM
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it
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based on hardware design. If user use 1.8V flash and 1.8V psram,
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this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based
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on hardware design. If user use 1.8V flash and 1.8V psram, this
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value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on
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hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do
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not need to configure the clock IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config ESP32_SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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range 0 33
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default 7
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help
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This value is ignored unless flash mode is set to DIO or DOUT and
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the SPI flash pins have been overriden by setting the eFuses
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SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4
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Quad I/O data pins. The WP pin (aka ESP32 pin "SD_DATA_3" or SPI
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flash pin "IO2") is not specified in eFuse. And the psram only
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has QPI mode, the WP pin is necessary, so we need to configure
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this value here.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be
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set as the value configured in bootloader.
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For ESP32-PICO chip, the default value of this config should be 7.
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endif # ESP32_PSRAM
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endif # ARCH_BOARD_ESP32CORE
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