77 lines
3.2 KiB
C
77 lines
3.2 KiB
C
/****************************************************************************
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* arch/risc-v/include/fe310/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_FE310_IRQ_H
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#define __ARCH_RISCV_INCLUDE_FE310_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Map RISC-V exception code to NuttX IRQ */
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/* Machine Global External Interrupt */
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#define FE310_IRQ_UART0 (RISCV_IRQ_MEXT + 3)
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#define FE310_IRQ_UART1 (RISCV_IRQ_MEXT + 4)
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#define FE310_IRQ_GPIO0 (RISCV_IRQ_MEXT + 8)
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#define FE310_IRQ_GPIO1 (RISCV_IRQ_MEXT + 9)
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#define FE310_IRQ_GPIO2 (RISCV_IRQ_MEXT + 10)
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#define FE310_IRQ_GPIO3 (RISCV_IRQ_MEXT + 11)
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#define FE310_IRQ_GPIO4 (RISCV_IRQ_MEXT + 12)
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#define FE310_IRQ_GPIO5 (RISCV_IRQ_MEXT + 13)
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#define FE310_IRQ_GPIO6 (RISCV_IRQ_MEXT + 14)
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#define FE310_IRQ_GPIO7 (RISCV_IRQ_MEXT + 15)
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#define FE310_IRQ_GPIO8 (RISCV_IRQ_MEXT + 16)
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#define FE310_IRQ_GPIO9 (RISCV_IRQ_MEXT + 17)
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#define FE310_IRQ_GPIO10 (RISCV_IRQ_MEXT + 18)
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#define FE310_IRQ_GPIO11 (RISCV_IRQ_MEXT + 19)
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#define FE310_IRQ_GPIO12 (RISCV_IRQ_MEXT + 20)
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#define FE310_IRQ_GPIO13 (RISCV_IRQ_MEXT + 21)
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#define FE310_IRQ_GPIO14 (RISCV_IRQ_MEXT + 22)
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#define FE310_IRQ_GPIO15 (RISCV_IRQ_MEXT + 23)
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#define FE310_IRQ_GPIO16 (RISCV_IRQ_MEXT + 24)
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#define FE310_IRQ_GPIO17 (RISCV_IRQ_MEXT + 25)
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#define FE310_IRQ_GPIO18 (RISCV_IRQ_MEXT + 26)
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#define FE310_IRQ_GPIO19 (RISCV_IRQ_MEXT + 27)
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#define FE310_IRQ_GPIO20 (RISCV_IRQ_MEXT + 28)
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#define FE310_IRQ_GPIO21 (RISCV_IRQ_MEXT + 29)
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#define FE310_IRQ_GPIO22 (RISCV_IRQ_MEXT + 30)
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#define FE310_IRQ_GPIO23 (RISCV_IRQ_MEXT + 31)
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#define FE310_IRQ_GPIO24 (RISCV_IRQ_MEXT + 32)
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#define FE310_IRQ_GPIO25 (RISCV_IRQ_MEXT + 33)
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#define FE310_IRQ_GPIO26 (RISCV_IRQ_MEXT + 34)
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#define FE310_IRQ_GPIO27 (RISCV_IRQ_MEXT + 35)
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#define FE310_IRQ_GPIO28 (RISCV_IRQ_MEXT + 36)
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#define FE310_IRQ_GPIO29 (RISCV_IRQ_MEXT + 37)
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#define FE310_IRQ_GPIO30 (RISCV_IRQ_MEXT + 38)
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#define FE310_IRQ_GPIO31 (RISCV_IRQ_MEXT + 39)
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/* Total number of IRQs */
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#define NR_IRQS (FE310_IRQ_GPIO31 + 1)
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#endif /* __ARCH_RISCV_INCLUDE_FE310_IRQ_H */
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