115 lines
5.0 KiB
Plaintext
115 lines
5.0 KiB
Plaintext
/****************************************************************************
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* boards/arm/stm32l4/nucleo-l496zg/scripts/memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
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* be accessed from either the AXIM interface at address 0x0800:0000 or from
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* the ITCM interface at address 0x0020:0000.
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*
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* Additional information, including the option bytes, is available at at
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* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
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*
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* In the STM32F746NGH6, two different boot spaces can be selected through
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* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
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* BOOT_ADD1 option bytes:
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*
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* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
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* ST programmed value: Flash on ITCM at 0x0020:0000
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* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
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* ST programmed value: System bootloader at 0x0010:0000
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*
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* NuttX does not modify these option bytes. On the unmodified STM32F746G
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* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
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* to address 0x0020:0000 in ITCM FLASH.
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*
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* The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
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* SRAM is split up into three blocks:
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*
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* 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
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* 2) 240Kb of SRAM1 beginning at address 0x2001:0000
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* 3) 16Kb of SRAM2 beginning at address 0x2004:c000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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*
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* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
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* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
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* should fit into 64KB and, of course, can be optimized as needed (See
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* also boards/stm32f746g-disco/scripts/kernel-space.ld). Allowing the
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* additional does permit addition debug instrumentation to be added to the
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* kernel space without overflowing the partition.
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*
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* Alignment of the user space FLASH partition is also a critical factor:
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* The user space FLASH partition will be spanned with a single region of
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* size 2**n bytes. The alignment of the user-space region must be the same.
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* As a consequence, as the user-space increases in size, the alignment
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* requirement also increases.
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*
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* This alignment requirement means that the largest user space FLASH region
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* you can have will be 512KB at it would have to be positioned at
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* 0x08800000. If you change this address, don't forget to change the
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* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
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* the check in kernel/userspace.c.
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*
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* For the same reasons, the maximum size of the SRAM mapping is limited to
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* 4KB. Both of these alignment limitations could be reduced by using
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* multiple regions to map the FLASH/SDRAM range or perhaps with some
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* clever use of subregions.
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*
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* A detailed memory map for the 112KB SRAM region is as follows:
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*
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* 0x20001 0000: Kernel .data region. Typical size: 0.1KB
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* ------- ---- Kernel .bss region. Typical size: 1.8KB
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* 0x20001 0800: Kernel IDLE thread stack (approximate). Size is
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* determined by CONFIG_IDLETHREAD_STACKSIZE and
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* adjustments for alignment. Typical is 1KB.
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* ------- ---- Padded to 4KB
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* 0x20001 1000: User .data region. Size is variable.
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* ------- ---- User .bss region Size is variable.
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* 0x20001 2000: Beginning of kernel heap. Size determined by
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* CONFIG_MM_KERNEL_HEAPSIZE.
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* ------- ---- Beginning of user heap. Can vary with other settings.
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* 0x20004 c000: End+1 of SRAM1
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*/
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MEMORY
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{
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/* ITCM boot address */
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itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
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/* 1024KB FLASH */
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kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
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uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
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xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
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/* 240KB of contiguous SRAM1 */
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ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K
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usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K
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xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K
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/* DTCM SRAM */
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
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}
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