#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_RISCV
comment "RISC-V Options"

choice
	prompt "RISC-V chip selection"
	default ARCH_CHIP_NR5

config ARCH_CHIP_FE310
	bool "SiFive FE310"
	select ARCH_RV32IM
	---help---
		SiFive FE310 processor (E31 RISC-V Core with MAC extensions).

config ARCH_CHIP_K210
	bool "Kendryte K210"
	select ARCH_RV64GC
	select ARCH_HAVE_TESTSET
	select ARCH_HAVE_MULTICPU
	select ARCH_GLOBAL_IRQDISABLE
	---help---
		Kendryte K210 processor (RISC-V 64bit core with GC extensions)

config ARCH_CHIP_NR5
	bool "NEXT NanoRisc5"
	select ARCH_RV32IM
	---help---
		NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores).

config ARCH_CHIP_GAP8
	bool "GreenwavesTechnologies GAP8"
	select ARCH_RV32IM
	---help---
		GreenwavesTechnologies GAP8 features a 1+8-core RI5CY DSP-like
		processor, which originally comes from the ETH PULP platform.

endchoice

config ARCH_RV32I
	bool
	default n

config ARCH_RV32IM
	bool
	default n

config ARCH_RV64GC
	bool
	default n

config ARCH_FAMILY
	string
	default "rv32im"	if ARCH_RV32IM
	default "rv64gc"	if ARCH_RV64GC

config ARCH_CHIP
	string
	default "fe310"		if ARCH_CHIP_FE310
	default "k210"		if ARCH_CHIP_K210
	default "nr5m100"	if ARCH_CHIP_NR5
	default "gap8"		if ARCH_CHIP_GAP8

config NR5_MPU
	bool "MPU support"
	default n
	depends on ARCH_HAVE_MPU
	select ARCH_USE_MPU
	---help---
		Build in support for the RISC-V Memory Protection Unit (MPU).
		Check your chip specifications first; not all RISC-V architectures
		support the MPU.

if ARCH_RV32IM
source arch/risc-v/src/rv32im/Kconfig
endif
if ARCH_RV64GC
source arch/risc-v/src/rv64gc/Kconfig
endif
if ARCH_CHIP_FE310
source arch/risc-v/src/fe310/Kconfig
endif
if ARCH_CHIP_K210
source arch/risc-v/src/k210/Kconfig
endif
if ARCH_CHIP_NR5
source arch/risc-v/src/nr5m100/Kconfig
endif
if ARCH_CHIP_GAP8
source arch/risc-v/src/gap8/Kconfig
endif

endif