#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_XTENSA

choice
	prompt "XTENSA architecture selection"
	default ARCH_CHIP_ESP32

config ARCH_CHIP_ESP32
	bool "Espressif ESP32"
	select ARCH_FAMILY_LX6
	select XTENSA_HAVE_INTERRUPTS
	select ARCH_HAVE_FPU
	select ARCH_HAVE_MPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_TEXT_HEAP
	select ARCH_HAVE_SDRAM
	select ARCH_HAVE_RESET
	select ARCH_HAVE_BOOTLOADER
	select ARCH_HAVE_TESTSET
	select ARCH_VECNOTIRQ
	select LIBC_ARCH_MEMCPY if BUILD_FLAT
	select LIBC_ARCH_MEMCHR if BUILD_FLAT
	select LIBC_ARCH_MEMCMP if BUILD_FLAT
	select LIBC_ARCH_MEMMOVE if BUILD_FLAT
	select LIBC_ARCH_MEMSET if BUILD_FLAT
	select LIBC_ARCH_STRCHR if BUILD_FLAT
	select LIBC_ARCH_STRCMP if BUILD_FLAT
	select LIBC_ARCH_STRCPY if BUILD_FLAT
	select LIBC_ARCH_STRLCPY if BUILD_FLAT
	select LIBC_ARCH_STRNCPY if BUILD_FLAT
	select LIBC_ARCH_STRLEN if BUILD_FLAT
	select LIBC_ARCH_STRNLEN if BUILD_FLAT
	---help---
		The ESP32 is a dual-core system from Espressif with two Harvard
		architecture Xtensa LX6 CPUs. All embedded memory, external memory
		and peripherals are located on the data bus and/or the instruction
		bus of these CPUs. With some minor exceptions, the address mapping
		of two CPUs is symmetric, meaning they use the same addresses to
		access the same memory.

		The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
		"application"), however for most purposes the two CPUs are
		interchangeable.

config ARCH_CHIP_ESP32S2
	bool "Espressif ESP32-S2"
	select ARCH_FAMILY_LX7
	select XTENSA_HAVE_INTERRUPTS
	select ARCH_HAVE_TEXT_HEAP
	select ARCH_HAVE_SDRAM
	select ARCH_HAVE_RESET
	select ARCH_HAVE_BOOTLOADER
	select ARCH_VECNOTIRQ
	select LIBC_ARCH_ATOMIC
	select LIBC_ARCH_MEMCPY
	select LIBC_ARCH_MEMCHR
	select LIBC_ARCH_MEMCMP
	select LIBC_ARCH_MEMMOVE
	select LIBC_ARCH_MEMSET
	select LIBC_ARCH_STRCHR
	select LIBC_ARCH_STRCMP
	select LIBC_ARCH_STRCPY
	select LIBC_ARCH_STRLCPY
	select LIBC_ARCH_STRNCPY
	select LIBC_ARCH_STRLEN
	select LIBC_ARCH_STRNLEN
	---help---
		ESP32-S2 is a truly secure, highly integrated, low-power, 2.4 GHz Wi-Fi
		Microcontroller SoC supporting Wi-Fi HT40 and having 43 GPIOs.
		Based on an Xtensa single-core 32-bit LX7 processor, it can be clocked
		at up to 240 MHz.

config ARCH_CHIP_ESP32S3
	bool "Espressif ESP32-S3"
	select ARCH_FAMILY_LX7
	select XTENSA_HAVE_INTERRUPTS
	select ARCH_HAVE_FPU
	select ARCH_HAVE_MPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_TEXT_HEAP
	select ARCH_HAVE_SDRAM
	select ARCH_HAVE_RESET
	select ARCH_HAVE_BOOTLOADER
	select ARCH_HAVE_TESTSET
	select ARCH_VECNOTIRQ
	select LIBC_ARCH_MEMCPY if BUILD_FLAT
	select LIBC_ARCH_MEMCHR if BUILD_FLAT
	select LIBC_ARCH_MEMCMP if BUILD_FLAT
	select LIBC_ARCH_MEMMOVE if BUILD_FLAT
	select LIBC_ARCH_MEMSET if BUILD_FLAT
	select LIBC_ARCH_STRCHR if BUILD_FLAT
	select LIBC_ARCH_STRCMP if BUILD_FLAT
	select LIBC_ARCH_STRCPY if BUILD_FLAT
	select LIBC_ARCH_STRLCPY if BUILD_FLAT
	select LIBC_ARCH_STRNCPY if BUILD_FLAT
	select LIBC_ARCH_STRLEN if BUILD_FLAT
	select LIBC_ARCH_STRNLEN if BUILD_FLAT
	---help---
		ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz.
		Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz,
		802.11 b/g/n Wi-Fi and Bluetooth 5 (LE) connectivity that provides long-range
		support.

config ARCH_CHIP_XTENSA_CUSTOM
	bool "Custom XTENSA chip"
	select ARCH_CHIP_CUSTOM
	---help---
		Select this option if there is no directory for the chip under arch/xtensa/src/.

endchoice # XTENSA chip selection

config XTENSA_HAVE_ICACHE
	bool
	default n

config XTENSA_HAVE_DCACHE
	bool
	default n

config XTENSA_HAVE_ICACHE_LOCK
	bool
	default n

config XTENSA_HAVE_DCACHE_LOCK
	bool
	default n

config XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
	bool
	default n

config XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
	bool
	default n

config XTENSA_ICACHE
	bool "Use I-Cache"
	default n
	depends on XTENSA_HAVE_ICACHE
	select ARCH_ICACHE
	---help---
		Enable Xtensa I-Cache

config XTENSA_DCACHE
	bool "Use D-Cache"
	default n
	depends on XTENSA_HAVE_DCACHE
	select ARCH_DCACHE
	---help---
		Enable Xtensa D-Cache

config XTENSA_ICACHE_LOCK
	bool "Use I-Cache lock & unlock feature"
	default n
	depends on XTENSA_HAVE_ICACHE
	depends on XTENSA_HAVE_ICACHE_LOCK
	select ARCH_ICACHE_LOCK
	---help---
		Enable Xtensa I-Cache lock & unlock feature

config XTENSA_DCACHE_LOCK
	bool "Use D-Cache lock & unlock feature"
	default n
	depends on XTENSA_HAVE_DCACHE
	depends on XTENSA_HAVE_DCACHE_LOCK
	select ARCH_DCACHE_LOCK
	---help---
		Enable Xtensa D-Cache lock & unlock feature

config XTENSA_ONESHOT
	bool "Xtensa oneshot lower half driver"
	default n
	depends on ONESHOT
	---help---
		Enable Xtensa oneshot driver.

config ARCH_FAMILY_LX6
	bool
	default n
	---help---
		Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
		The LX6 is a configurable and extensible processor core.

config ARCH_FAMILY_LX7
	bool
	default n
	---help---
		Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU).
		The LX7 is a configurable and extensible processor core.

config ARCH_CHIP
	string
	default "esp32" if ARCH_CHIP_ESP32
	default "esp32s2" if ARCH_CHIP_ESP32S2
	default "esp32s3" if ARCH_CHIP_ESP32S3

config XTENSA_CP_LAZY
	bool "Lazy co-processor state restoration"
	default n
	depends on EXPERIMENTAL
	---help---
		NuttX logic saves and restores the co-processor enabled (CPENABLE)
		register on each context switch.  This has disadvantages in that (1)
		co-processor context will be saved and restored even if the co-
		processor was never used, and (2) tasks must explicitly enable and
		disable co-processors.

		An alternative, "lazy" co-processor state restore is enabled with
		this option.  That logic works like as follows:

		a. CPENABLE is set to zero on each context switch, disabling all co-
		   processors.
		b. If/when the task attempts to use the disabled co-processor, an
		   exception occurs
		c. The co-processor exception handler re-enables the co-processor.

config XTENSA_USE_OVLY
	bool
	default n
	---help---
		Enable code overlay support. This option is currently unsupported.

config XTENSA_CP_INITSET
	hex "Default co-processor enables"
	default 0x0001
	range 0 0xffff
	depends on !XTENSA_CP_LAZY
	---help---
		Co-processors may be enabled on a thread by calling xtensa_coproc_enable()
		and disabled by calling xtensa_coproc_disable().  Some co-processors
		should be enabled on all threads by default.  That set of co-processors
		is provided by CONFIG_XTENSA_CP_INITSET.  Each bit corresponds to one
		coprocessor with the same bit layout as for the CPENABLE register.

config XTENSA_DUMPBT_ON_ASSERT
	bool "Dump backtrace on assertions"
	default y
	depends on DEBUG_ALERT
	---help---
		Enable a backtrace dump on assertions.

config XTENSA_BTDEPTH
	int "Backtrace depth"
	default 50
	depends on XTENSA_DUMPBT_ON_ASSERT
	---help---
		This is the depth of the backtrace.

config XTENSA_INTBACKTRACE
	bool "Full backtrace from interrupts"
	default n
	depends on XTENSA_DUMPBT_ON_ASSERT
	---help---
		Add necessary logic to be able to have a full backtrace from an interrupt context.

config XTENSA_IMEM_USE_SEPARATE_HEAP
	bool "Use a separate heap for internal memory"
	select ARCH_HAVE_EXTRA_HEAPS
	default n
	---help---
		This is a separate internal heap that's used by drivers when certain operations
		are not possible with the provided buffer(s).
		Mainly, when the provided buffer comes from external RAM and a DMA or flash
		operation is going to be performed.
		This separate heap will be part of the internal DRAM.

config XTENSA_IMEM_REGION_SIZE
	hex "DRAM region size for internal use"
	depends on XTENSA_IMEM_USE_SEPARATE_HEAP
	default 0x18000

config XTENSA_EXTMEM_BSS
	bool "Allow BSS section in external memory"
	default n
	---help---
		Adds a section and an attribute that allows to force variables into
		the external memory.

config XTENSA_SEMIHOSTING_HOSTFS
	bool "Semihosting HostFS"
	depends on FS_HOSTFS
	---help---
		Mount HostFS through semihosting.

		This doesn't support some directory operations like readdir because
		of the limitations of semihosting mechanism.

if XTENSA_SEMIHOSTING_HOSTFS

config XTENSA_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
	bool "Cache coherence in semihosting hostfs"
	depends on ARCH_DCACHE
	---help---
		Flush & Invalidte cache before & after sim call.

endif

choice
	prompt "Toolchain Selection"
	default XTENSA_TOOLCHAIN_ESP

config XTENSA_TOOLCHAIN_XCC
	bool "Xtensa Toolchain use GCC as front end"
	select ARCH_TOOLCHAIN_GNU

config XTENSA_TOOLCHAIN_XCLANG
	bool "Xtensa Toolchain use CLANG as front end"
	select ARCH_TOOLCHAIN_GNU

config XTENSA_TOOLCHAIN_ESP
	bool "ESP toolchain for xtensa"
	select ARCH_TOOLCHAIN_GNU

endchoice

source "arch/xtensa/src/lx6/Kconfig"

if ARCH_CHIP_ESP32
source "arch/xtensa/src/esp32/Kconfig"
endif

source "arch/xtensa/src/lx7/Kconfig"

if ARCH_CHIP_ESP32S2
source "arch/xtensa/src/esp32s2/Kconfig"
endif

if ARCH_CHIP_ESP32S3
source "arch/xtensa/src/esp32s3/Kconfig"
endif

endif # ARCH_XTENSA