compile error log:
common/arm64_arch_timer.c: In function 'arm64_tick_max_delay':
common/arm64_arch_timer.c:178:12: error: conversion from 'long unsigned int' to 'clock_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Werror=overflow]
178 | *ticks = UINT64_MAX;
| ^~~~~~~~~~
Signed-off-by: hujun5 <hujun5@xiaomi.com>
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1. arm64/makefile: preprocess link script to make configure more flexibly
2. arm64/EXTRA_LIBS: link all staging library
Signed-off-by: chao an <anchao@xiaomi.com>
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In the interrupt context, we should first save the interrupt context and modify the interrupt register
to execute the signal processing program immediately after exiting the current interrupt
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. Get the value of sp from dump regs when an exception occurs,
to avoid getting the value of fp from up_getsp and causing
incomplete stack printing.
2. Determine which stack the value belongs to based on the value
of SP to avoid false reports of stack overflow
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
the PR submit a base method to see performance counts for
the FPU with NuttX procfs
Please read README.txt at chapter of FPU Support and Performance
for more information
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c
2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON
3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.
4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead
5 In arm64_tick_cancel func，The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles
6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:
1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
and the running task obtained is still task1, but
the actual task that generated the exception is task2.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
perf interface related code.
- Support for pmu init under smp.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Summary:
add arm64_serialinit/arm64_earlyserialinit function prototype
to arm64_internal.h as common function for arm64 based chip.
Testing with ostest in SP and SMP
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:
- GICv3 interrupt controllers for ARMv8-r
- PL011 UART controller(FVP)
Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
board readme.txt
TODO: merge PL011 UART driver to common place
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
-reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
-reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
every CPU at boot EL2 stage.
For some platform, the bootloader or hypervisor will do that at
the EL2 stage, but not all.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:
1. ARM Single Security State Support, ARMv8-R support only single
security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
and system register for EL3 is not accessible(gcc will failed when
access these registers)
3. add base MPU configure for the platform.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summory
This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
Add configure option for it.
Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.
Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
the opton to be configured with menuconfig
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
This is preparation for moving address environments out of the group
structure into the tcb.
Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
This is fixed by making a stack frame to the user stack and copying it
there.
- If the signal handler uses a system call, the kernel stack was completely
and unconditionally destroyed, resulting in a crash in the user application
There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.
Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).
### Modified Files
`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt
`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH
`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
hujun5