4fa6106b57
Fix some compile problems found in build testing.
2017-08-12 14:28:27 -06:00
1f989af845
Update TODO list; SAMv7 XDMAC: Remove and unused global array.
2017-08-12 12:26:13 -06:00
4b6f0149ec
Eliminate a warning found in build testing.
2017-08-12 11:14:11 -06:00
6bae133e74
Fix two warnings found in build testing.
2017-08-12 11:09:48 -06:00
bd7c84b23e
Remove CONFIG_NETDEV_MULTINIC. This increases code size by a little, but greatly reduces the complexity of the network code.
2017-08-08 14:24:12 -06:00
22dfa875fc
I discovered while working on the SAMV7 mcan driver that the implementation of the CAN error handling is suboptimal. In the current implementation the following errors are implemented as pending errors:
...
* Receiving
* MCAN_INT_STE (Stuff Error)
More than 5 equal bits in a sequence occurred.
* MCAN_INT_CRCE (CRC Error)
Received CRC did not match the calculated CRC.
* MCAN_INT_RF0L (Receive FIFO 0 Message Lost)
Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero.
* MCAN_INT_RF1L (Receive FIFO 1 Message Lost)
Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero.
* Sending
* MCAN_INT_BE (Bit Error)
Device wanted to send a rec / dom level, but monitored bus level was dominant / recessive.
* MCAN_INT_TEFL (Tx Event FIFO Element Lost)
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
* General
* MCAN_INT_MRAF (Message RAM Access Failure)
The flag is set, when the Rx Handler
* has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
* was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation mode (see Section 47.5.1.5). To leave Restricted Operation mode, the processor has to reset MCAN_CCCR.ASM.
* MCAN_INT_ELO (Error Logging Overflow)
Overflow of CAN Error Logging Counter occurred.
The listed errors are not pending, the errors occurred and are gone directly afterwards. This commit changes the described behavior and simplifies the handling of CAN errors.
2017-08-07 10:31:04 -06:00
4cbde22992
I'm working on bringing up USB full-speed support on STM32F405. My board does not include a USB power switch, VBus sensing, over current detection, or ID pin.
...
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control. I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet. The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.
These changes let a USB mouse enumerate on my platform if it's plugged in on power-up. Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding. Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything. I'm hoping my issue is something simple I overlooked in configuration.
I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
2017-08-07 10:24:31 -06:00
b1f50490bd
MTD: Add driver for Macronix QuadSPI flash memory
2017-08-06 10:51:17 -06:00
4cc13f8d94
Simulator: x86 stack needs to be aligned to 16-byte boundaries.
2017-08-04 07:03:39 -06:00
42b3ee4cfc
Fix a few errors that crept in with my review changes.
2017-08-02 09:19:29 -06:00
5f2d4b8f84
Changes from review of commit e851a24329
2017-08-02 08:26:08 -06:00
e851a24329
arch/arm/src/lc823450: Initial support for ON Semiconductor LC823450
...
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2017-08-02 21:09:43 +09:00
55e9c8990c
stm32_rcc: code style
2017-08-01 16:25:19 +02:00
a4e97d5daf
Added functions for DSI clock source selection
2017-08-01 16:24:48 +02:00
05ea22e9ab
STM32F7: Fix for coding standard violations that came in with cd3ca1140e -- missed a file last time
2017-07-31 18:36:38 -06:00
5f4fdb42be
STM32F7: Fix for coding standard violations that came in with cd3ca1140e
2017-07-31 18:35:37 -06:00
604a6dc0fa
improved help text
2017-08-01 01:23:28 +02:00
bdee01f492
added function for reset
2017-08-01 01:23:28 +02:00
0947b31fbb
STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
2017-08-01 01:23:28 +02:00
9d56dbb403
comment corrected
2017-08-01 01:23:28 +02:00
63bce1fc34
no board specific dithering values used; corrected comment; corrected dithering init
2017-08-01 01:23:28 +02:00
ec95720d13
corrected LIPOS/LIPCR calculation
2017-08-01 01:23:28 +02:00
28a53d8e25
change only polarity bits in LTDC_GCR
2017-08-01 01:23:28 +02:00
5de2468521
comments corrected
2017-08-01 01:23:28 +02:00
69aca28e87
commented
2017-08-01 01:23:28 +02:00
ec43001d91
HEAP2 depends on CONFIG_ARCH_HAVE_HEAP2, not on particular FMC RAM type
2017-08-01 01:23:28 +02:00
777b17928f
corrected register debugging
2017-08-01 01:23:28 +02:00
1944ab6f9b
added missing config option for register value debugging
2017-08-01 01:23:28 +02:00
dc392a6c68
enable APB2 DSI clock
2017-08-01 01:23:28 +02:00
59b9983d97
Simulator: Protect a few more NuttX symbols from collisions with host symbols.
2017-07-31 15:41:31 -06:00
20dc5ad3b4
STM32L1: add base address for TIM11
...
STM32L4 PWR: correct PWR_SR2 REGLPS and REGLPF bits, add port I registers. Also remove duplicate section from Kconfig
2017-07-31 07:32:43 -06:00
a420c0f369
To use an external oscillator module (not just a crystal) with the STM32F4, one needs to enable the HSEBYP bit in the RCC_CR register. This change allows an integrator to define STM32_RCC_CR_HSEBYP in their board.h file if they want this configuration.
2017-07-30 06:22:30 -06:00
47791442a0
Squashed commit of the following:
...
commit 3fcf84a9a2673e1e1466ce5b114d7b73c257e515
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 12:00:31 2017 -0600
Spirit: Brings in the last of the PktCommon interfaces.
commit d26ebd901ba4ba84910e99b4e728b98c30fa4c0b
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:54:52 2017 -0600
Spirit: Add a few more PktCommon interfaces.
commit b5cb8041d50233a4abb8fb4d1dcef5428ae2c2b2
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:33:31 2017 -0600
libc/termios: Remember block comments before empty file sections.
commit 0fcab2c1c8c74442d40bd5e8c6af50a34f8a5821
Author: Sebastien Lorquet <sebastien@lorquet.fr>
Date: Fri Jul 28 09:31:00 2017 -0600
tcdrain implementation based on a new term ioctl
commit 797d4adf7d41068c671f0217d369b797b269de1a
Author: Stefan Kolb <Stefan.Kolb@avat.de>
Date: Fri Jul 28 09:19:04 2017 -0600
We discovered a problem with the samv7 mcan driver which results, under some circumstances, in a very high CPU load.
The problem occurs, and is easily reproducible, if the device is connected to a CAN network with a wrongly configured CAN speed (baud rate). In our tests we set the CAN speed of the device to 1000000 and the speed of the other CAN nodes to 500000. The device is restarted and sends a CANopen “bootup message” to the CAN network. This results in huge amount of errors messages on the CAN bus, probably because of the CAN feature for acknowledging error messages. The error messages can’t be read by the device because of the misconfigured CAN speed, instead the CAN chip reports lots of errors, which are reported to the application which uses the CAN driver (CONFIG_CAN_ERRORS is enabled).
The CAN errors are reported from the CAN chip via interrupts and thus the interrupt load is very high in this scenario. To fix the problem the driver now disables each RX error interrupt after it is occurred. The RX error interrupts are turned back on if at least one CAN message is received successfully.
commit e298f48e96d9e34017dcab8e4d87032862ae9322
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:06:26 2017 -0600
Spirit: Bring in PktStack interfaces.
commit 4a0f00a7058312dcf6ac392689b9f69112f613ec
Merge: 855cf97130 b458934ac4f287cc25d6598386ef90c9ff8cbab92fc0fbcf7e6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-28 12:01:05 -06:00
5f31999b75
Trivial fix to spacing
2017-07-27 11:50:59 -06:00
28eab902d0
No FSMC, only FMC for STM32F7
2017-07-27 18:27:01 +02:00
2fc0fbcf7e
Squashed commit of the following:
...
commit 89e9d426e91c056e659fccf5e5c4392618f8f777
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:44:19 2017 -0600
Update some comments
commit 9c5d8a5833350006ed389e898b11c8c8a20e5f4f
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:15:54 2017 -0600
Spirit: Rename drivers/wireless/spirit/src to lib. Move Spirit network driver out of IEEE802.15.4 into drivers/wireless/spirit/drivers
commit cabc0ec9e6eb558dcb715ab17264383aa0105e7a
Merge: 87b616414a 6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-24 16:46:30 -06:00
f4e46b0da7
Missed part of 2319ea53a9. Was still getting the warning.
2017-07-22 10:55:54 -06:00
2319ea53a9
STM32L4: Eliminate a warning about implicit definition of function. While we are at it, let's improve the naming a little too.
2017-07-22 09:53:29 -06:00
2e7961cc55
sim arch: fix mkdir issue in GNU target
2017-07-22 09:01:24 -06:00
53a8cb734b
sim arch: poll for TX frames to speed up driver
2017-07-22 09:01:24 -06:00
63c9f1a86e
sim arch: Add non blocking read to devconsole driver
2017-07-22 09:01:24 -06:00
f6c1d59531
stm32_hrtim: add slave timers private data, fix some bad definitions, some asserions
2017-07-22 15:14:59 +02:00
c3b552e072
Minor cosmetic updates from review of last PR.
2017-07-20 07:39:57 -06:00
a20c3b17ce
warning message when using DSI (for debugging)
2017-07-19 20:39:27 +02:00
7b07471ece
documentation update to f7
2017-07-19 19:14:50 +02:00
6d29a04752
naming errors/inconsitencies/typos
2017-07-19 19:14:49 +02:00
1241960d4a
STM32F7: Switch from CCM to DTCM
2017-07-19 19:07:53 +02:00
071b2dda28
compileable with LTDC_INTERFACE and LTDC_USE_DSI
2017-07-19 19:07:53 +02:00
e67ba8c88d
option for DSI output
2017-07-19 19:07:53 +02:00
d590ba7ab2
do not enforce CONFIG_STM32_CCMEXCLUDE for CONFIG_ARCH_CHIP_STM32F7, macro rename STM32 -> STM32F7, #include corrections
2017-07-19 19:07:53 +02:00
Gregory Nutt