7b789f57ac
Review of previous commit
2017-03-30 12:28:40 -06:00
95cbbf552b
Change STM32 tickless to use only one timer
2017-03-30 10:40:05 -07:00
5577f58458
STM32 RNG: Fix semaphore initial value and disable priority inheritance
2017-03-29 07:12:19 -06:00
9f3b24a4a1
STM32 F7: add stm32 RNG support. This is copied from stm32l4. Tested on STM32F746ZG board.
2017-03-29 07:08:10 -06:00
92da8068ed
Merge branch 'master' of bitbucket.org:nuttx/nuttx
2017-03-26 06:57:35 -06:00
62f9ae0852
Merged in raiden00/nuttx (pull request #300 )
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STM32 COMP cosmetics
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-03-26 12:21:32 +00:00
f3367233b6
stm32_comp.c: typo
2017-03-26 09:36:53 +02:00
c1090164f5
stm32/Kconfig: update COMP and OPAMP definitions
2017-03-26 09:34:17 +02:00
6594c65a77
stm32_comp.c: cosmetic
2017-03-26 09:30:23 +02:00
7d57a2b2bd
Trivial changes from review of last PR.
2017-03-25 10:38:41 -06:00
c174074dd8
Merged in raiden00/nuttx (pull request #299 )
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Add COMP character driver
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-03-25 16:29:02 +00:00
602546f852
Minor typo fix
2017-03-25 10:23:53 -06:00
a806aedb13
STM32F33: Support for COMP character driver
2017-03-25 16:57:43 +01:00
61ff3c6b84
I needed to use DS3231, I remember that in past it worked ok, but now for stm32f4xx is used another driver (chip specific, stm32f40xxx_i2c.c) and DS3231 driver doesn't work. After investigating a problem I found that I2C driver (isr routine) has a few places there it sends stop bit even if not all messages are managed. So, e.g., removing stm32_i2c_sendstop ( #1744 ) and adding stm32_i2c_sendstart after data reading helps to make DS3231 working. Verified by David Sidrane.
2017-03-24 06:44:33 -06:00
82a84a8d98
Merged nuttx/nuttx into master
2017-03-24 11:40:09 +03:00
4c6680df99
Merged in no1wudi/nuttx (pull request #291 )
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fix compile error when disabled the flash data cache corruption for stm32 f1xx
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-03-24 00:58:26 +00:00
fd76a3db05
fix spacing
2017-03-24 08:52:46 +08:00
5797e84893
Merged nuttx/nuttx into master
2017-03-24 08:40:40 +08:00
66910577be
stm322_flash:missing unlock on F1 HSI off path
2017-03-23 14:22:45 -10:00
7e3bec635b
stm32_i2c_alt:Move def of regval to top func def per CS
2017-03-23 11:50:37 -10:00
d25f8710d2
stm32f40xxx_i2c:Duplicate non CS dev of regval
2017-03-23 11:37:12 -10:00
f5cf22d871
stm32_i2c_alt:Duplicate non CS dev of regval
2017-03-23 11:36:44 -10:00
c2a1b719be
stm32_flash:Need conditinal on non F4 targets
2017-03-23 11:33:32 -10:00
9353ca6039
STM32 I2C: Do not allow CONFIG_I2C_POLLED and CONFIG_I2C_DMA
2017-03-23 11:24:18 -06:00
06af125e45
The interrupt occurs over the counter overflow
2017-03-23 17:34:45 +03:00
45f5d30e2e
fix compile error when disabled the flash data cache corruption for stm32 f1xx
2017-03-23 13:38:26 +08:00
c73b65c9b9
stm32f7:stm32_allocateheap.c There are 5 configurations
2017-03-22 23:56:54 +00:00
3fb0a00c35
Small changes from review of last PR. Plus spacing and typo fix.
2017-03-22 17:32:52 -06:00
947acd6c1a
Small changes from review of last PR
2017-03-22 15:53:12 -06:00
b9b4f184a7
stm32: Add workaround for flash data cache corruption on read-while-write
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This is a know hardware issue on some STM32 see the errata of your model
and if you make use of both memory banks you should enable it.
2017-03-22 13:14:19 -07:00
09f70c462d
stm32: Make up_progmem thread safe
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Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a semaphore and syncronize
access to Flash registers.
But for the semaphore to work it needs to be initialized so each
board needs call stm32_flash_initialize() on initialization, so
to avoid runtime problems it is only using semaphore and making
it thread safe if initialized, after all boards starts to call
stm32_flash_initialize() we can remove the boolean and the check.
2017-03-22 13:14:15 -07:00
80f56e75f9
stm32: Fix erase sector number for microcontrolers with more than 11 sectors
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Erase a sector from the second bank cause the bit 4 of SNB being set
but never unsed, so trying to erase a sector from the first bank
was acually eraseing a sector from the second bank.
2017-03-22 12:42:20 -07:00
7f2c4c4274
XMC4xxx: Add FPU support
2017-03-22 12:04:32 -06:00
3f3aa73b8f
XMC4xxx: USIC SCTR register, appears taht both WLE and FLE fields hold value - 1.
2017-03-21 17:51:55 -06:00
ea93357a1e
XMC4xxx: Fix a typo in the SCU header file
2017-03-21 17:05:47 -06:00
82a5dfddb4
The attached .patch implements DMA support for the stm32f4 I2C. Max and I have verified that it works on our systems.
2017-03-21 16:44:11 -06:00
343f7ceab2
XMC4xxx: Misc clock clean-up; PBDIV should be controllable from board.h
2017-03-21 15:05:17 -06:00
602bdd13fb
XMC4xxx: Fix a pin configuration problem. Fix some mispellings.
2017-03-21 11:24:04 -06:00
21a626878a
XMC4xxx: Clean up problems associated with USIC initialization. USIC still does not work in UART mode.
2017-03-21 10:55:52 -06:00
805a4f65e9
XMC4xxx: Fixes to HIB domain setup, GPIO pin configuration.
2017-03-21 09:31:44 -06:00
886dadae0a
XMC4xxx: Minor updates to naming and comments
2017-03-20 18:10:23 -06:00
b9e29d1083
XMC4xxx: Clean up memory map
2017-03-20 17:08:09 -06:00
4ba091933e
XMC4xxx: Fix for early bringup problems
2017-03-20 16:31:35 -06:00
3a91ba5264
XMC4xxx: Plug last holes to get a first, clean build.
2017-03-20 13:46:02 -06:00
985c137b78
XMC4xxx: Finishes system timer logic.
2017-03-20 13:20:31 -06:00
4519b679af
XMC4xxx: Finish code for USIC serial driver.
2017-03-20 12:47:26 -06:00
8a3422f837
XMC4xxx: Complete lowputc logic
2017-03-20 11:25:51 -06:00
7d6ee0f222
fix a typo
2017-03-20 09:50:27 +08:00
5df421488c
XMC4xxx: Add USIC baudrate calculation.
2017-03-19 18:11:38 -06:00
ae32905fe8
XMC4xxx: Simply some USIC logic, add USIC interface to disable a channel. Add USIC enable logic to UART configuration (a lot more to do there).
2017-03-19 17:06:44 -06:00
Gregory Nutt