This patch fixed userspace headers conflict. Architecture-related definition and API should not be exposed to users.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
reason:
Replace "inline" with "inline_function" for "up_interrupt_context" to ensure consistency with other arch
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. CONFIG_ARCH_COVERAGE has been replaced by CONFIG_SCHED_GCOV
2. Delete the SIM-specific GCOV_ALL configuration and change it to a universal configuration for all architectures
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Return 0 for CPU ID for any hart ID, and return the current Hart ID for
any CPU ID. At least these values are somewhat usable / meaningful in
non-SMP configurations.
MPFS implements external interrupt control on a per-hart basis i.e. there
are PLIC control registers for each hart separately. This means we need
a procedure to initialize such registers for each hart individually,
instead of only for the boot hart like it is now.
Fix this by implementing mpfs_plic_init_hart which can be called by each
hart as needed.
Note: it is not a good idea to initialize all harts from the boot hart,
as the boot hart may not know which harts are used by NuttX in AMP
configuration. It is better that the hart initializes itself.
Note: The hartid must be provided as explicit parameter, as it cannot
be queried via riscv_mhartid() yet; the per-cpu structure is initialized
later on which means riscv_mhartid() would return 0 for all harts except
the boot hart.
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).
Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI
Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
example for this is provided yet)
The function is supposed to return the physical hart ID. It is needed
for e.g. external interrupt acknowledgment (see mpfs_plic.c).
This offset is moved initially to up_cpu_index (which is also wrong, but
less wrong than the current implementation). Finally, a translation
between physical <-> logical shall be provided.
1. add IS_ALIGNED() definitions for NuttX;
2. replace all the ALIGN_UP() and ALIGN_DOWN() to use common
align implementation;
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Correct the alert message in `esp_setup_irq()` if
irq number allocation fails, the parameter number is not
matched with format specifier.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.
Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules
creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:
In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
from /nuttx/arch/risc-v/src/chip/chip.h:32,
from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
36 | #define SBI_EXT_BASE 0x00000010
and so forth...
Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
reason:
To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
after that we need to further implement "schedlock + spinlock".
changelist
1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
4 change up_cpu_pause_async to up_send_cpu_sgi
Signed-off-by: hujun5 <hujun5@xiaomi.com>
tools/configure.sh esp32c3-generic:wifi
wapi scan wlan0
has no return result after couple times
rootcause:
mq_timedsend() return failed because the time valid check error.
the ts_nsec is bigger than 1000000000.
esp_update_time() hasn't consider of the ns > 1s after the adding
calculation
Signed-off-by: ligd <liguiding1@xiaomi.com>
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Eren Terzioglu