5107104bbe
arch/sim: Model host signal as NuttX's interrupt
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-03 10:20:50 +08:00
5db11a275e
arch/sim: Mask and restore the host signal in irq_save and irq_restore
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to avoid the host signal process interrupt the execution of NuttX critical section
Signed-off-by: Sebastian Ene <nuttx@fitbit.com>
2020-09-03 10:20:50 +08:00
8ce0ff5ce4
arch/sim: Make up_internal.h includable in host environment
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to avoid the declaration repetition
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-08-21 18:09:19 +08:00
b330b3ac0c
arch/sim: Fix the linkage of up_irqinitialize mismatch
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include/arch/irq.h💯 20: note: previous declaration with ‘C++’ linkage
100 | static inline void up_irqinitialize(void)
| ^~~~~~~~~~~~~~~~
In file included from include/ctype.h:45,
from include/libcxx/ctype.h:38,
from include/libcxx/cctype:38,
from include/libcxx/cwctype:53,
from include/libcxx/cwchar:106,
from include/libcxx/string:510,
from libcxx/src/debug.cpp:13:
include/nuttx/arch.h:1343:6: error: conflicting declaration of ‘void up_irqinitialize()’ with ‘C’ linkage
1343 | void up_irqinitialize(void);
| ^~~~~~~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I0e0963a3465f9dabdaca6534a55b9c2c41f4bc64
2020-07-30 12:50:39 +09:00
4176a3828b
arch/sim: implement sim_getsp
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-07-09 13:51:09 +01:00
4fbbd2e3bf
arch: Move PRIxMAX and SCNxMAX definition to include/stdint.h
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like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
2020-06-10 08:24:47 +02:00
7758eb8658
arch: Define INTx_C and UINTx_C macro
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia50ea8764880fabd3d878c95328632c761be6b43
2020-06-10 08:24:47 +02:00
c2244a2382
Remove CONFIG_TLS
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A first step in implementing the user-space error is force TLS to be enabled at all times. It is no longer optional
2020-05-07 12:04:16 -06:00
bda24f09c2
libs/libc/tls/tls_getinfo.c: Add tls_get_info()
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Move the logic to get TLS information from an inline function to a normal function. For the unaligned case, it is probably too large to be inlined.
Also fixes some minor things from review of previous commits.
2020-05-05 18:56:33 +01:00
b7e7fba732
TLS_UNALIGNED ( #2 )
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* Implement the TLS_UNALIGNED
2020-05-05 18:56:33 +01:00
679b4fbee2
arch: Fix included directed -> included directly
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This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
e7d9260014
arch: Customize the typedef of size_t instead of intptr_t
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To ensure size_t same as toolchain definition in the first place and rename CXX_NEWLONG to ARCH_SIZET_LONG. The change also check whether __SIZE_TYPE__ exist before CONFIG_ARCH_SIZET_LONG so our definition can align with toolchain(gcc/clang) definition automatically.
2020-02-18 07:15:19 -06:00
76bbed07a4
Call up_irqinitialize from irq subsystem
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Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
2020-02-08 07:39:22 -06:00
80277d1630
Refine the preprocessor conditional guard style ( #190 )
2020-01-31 19:07:39 +01:00
68951e8d72
Remove exra whitespace from files ( #189 )
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* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
c840ac2496
arch/sim: Even though the simulation has no chips, it needs to have CONFIG_ARCH_CHIP and chip sub-directories. Otherwise, we would have to treat it as a special case in the build system.
2019-08-07 16:05:00 -06:00
eef2f4599e
Commit 933e9e407b broke the simulator on a 64-bit platform.
2019-07-29 14:34:29 -06:00
1e59d9dd14
armv7-a, armv7-r, armv7-m: Add atomic read-add-write and read-subtract-write functions.
2018-02-04 12:22:03 -06:00
48c27f8ffc
Simulator: Adds necessary functionality to build Simulator under ARM Linux. Tested only on Raspberry3. Currently setjmp/longjmp do not save/restore floating point registers. Patch provided by Bitbucket user nbkolchin.
2017-08-26 11:38:44 -06:00
9f7ba21f8a
Implement deferred IRQ locking. Adds support for simulator.
2016-12-23 11:28:43 -06:00
912fe06a86
Add architecture-specific inttypes.h
2016-10-27 16:01:38 -04:00
48fb97e7b5
More of the same cloned typo
2016-10-19 10:11:45 -06:00
56f2454c86
Fix names of pre-processor variables used in header file idempotence
2016-08-06 18:48:45 -06:00
d41008e220
Update some header commments
2016-08-06 18:16:31 -06:00
39e7d5431f
update gitignore
2016-06-24 16:29:15 -06:00
a74c19bbae
SIM: Add TLS support to to the simulator
2016-03-11 14:03:27 -06:00
83bc1c97c3
Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
2016-02-14 16:11:25 -06:00
b087cb7f9a
SIM: Add SMP idle thread setup logic
2016-02-11 12:16:19 -06:00
5e91bf9a03
SIM: Add a fake spinlock.h header file that may be useful someday for testing of SMP features
2016-02-10 10:33:37 -06:00
d7c5ff98f4
Fix a typo
2015-11-23 18:55:38 +00:00
edb1439d8f
Last change introduced warnings when CONFIG_SIM_M32=y; This fixes those warnings too
2015-11-23 12:44:59 -06:00
cae0c9a2e3
Standardize the width of all comment boxes in header files
2015-10-02 17:47:23 -06:00
36726b1bc4
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
29136e51cc
Clean up and review of header files for conformance to standards
2015-06-12 19:26:01 -06:00
ae15c6963c
Make some file section headers more consistent with standard
2015-04-08 08:04:12 -06:00
28a74ac02f
MM: Minimum memory allocation must to up to 32 if sizeof pointer is 8-bytes
2014-11-02 12:11:20 -06:00
48c76840a9
configs/sim/nsh/defconfig -- refresh, enable wall-time, dow builds natively in 64-bit mode
2014-10-03 08:44:42 -06:00
31049a203c
Add support for 64-bit lonjmp/setjmp in simulator platform
2014-10-03 08:23:57 -06:00
29406c0d20
Add option to select 64-bit build platform
2014-08-22 18:21:32 -06:00
d989807e76
uintptr_t should be 64-bits under Cygwin64
2014-08-22 15:18:55 -06:00
25d4ff745b
More trailing whilespace removal
2014-04-13 16:22:22 -06:00
1a07e950ea
Move LPC17xx IOCON register definitions from lpc17_gpio.h to lpc17_iocon.h; fix a few more .gitignore files
2013-04-04 18:12:44 -06:00
1694955188
Clone svn:ignore directory atributed to .gitignore files
2013-04-04 14:27:29 -06:00
cd20adb63d
Patches from Petteri Aimonen + stdbool and rand() changes for Freddie Chopin
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5415 42af7a65-404d-4744-a932-0658087f49c3
2012-12-07 16:00:56 +00:00
36df84c843
Email address change in nuttx/
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
2012-09-13 18:32:24 +00:00
faf4bad3f1
Change all values in all limits.h for all architectures to signed decimal; the hex values were not sign extending appropriate in most uses
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4911 42af7a65-404d-4744-a932-0658087f49c3
2012-07-05 23:45:57 +00:00
f37cd2e046
Remove user_initialize(); Make sure all integer types are signed that need to be
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3474 42af7a65-404d-4744-a932-0658087f49c3
2011-04-06 17:48:56 +00:00
434a24d88f
Stubs are working/Proxies are close
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3451 42af7a65-404d-4744-a932-0658087f49c3
2011-04-01 21:36:17 +00:00
a55fc5bb81
header file and file header clean-up
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3434 42af7a65-404d-4744-a932-0658087f49c3
2011-03-28 21:21:11 +00:00
6be18e43cf
Changing NuttX fixed size type names to C99 standard names -- things will be broken for awhile
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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2356 42af7a65-404d-4744-a932-0658087f49c3
2009-12-16 14:52:56 +00:00
Xiang Xiao