Commit Graph

42491 Commits

Author SHA1 Message Date
Alin Jerpelea a43650648e risc-V: remove ble defconfigs
By default the components with BSD license should be disabled

NOTE:
the BLUETOOTH components was enabled in a non bluetooth config

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Alin Jerpelea 5bc10ba9a6 nrf52832-mdk: remove sdc defconfig
By default the Bluetooth configuration is disabled due to BSD license

Please enable the use of BSD licenses and the Bluetooth config

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Alin Jerpelea c29cc7e241 stm32f4discovery: hciuart: remove hciuart defconfig
By default the components with BSD license should be disabled

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Alin Jerpelea 8119e1e8e0 sim: enable BSD components
By default the components with BSD license are disabled.

NOTE:
We are making an exception and enable the BSD components for
Simulator build to be able to thest the functionality.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Alin Jerpelea dc590e6414 tools: cxd56: update licenses to Apache
Sony has submitted the SGA and we can update the remaining licenses
to Apache

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Alin Jerpelea 29bfbf8769 License: add Bluetooth LE support to the license guard
If ALLOW_BSD_COMPONENTS is not enabled in the license setup,
Bluetooth LE support will be disabled

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
zhuyanlin 528d18ef26 libxx: rename NUTTX_LIBCXX
NUTTX_LIBCXX is only basic C++ support, do not support many c++
library function, NUTTX_NOCXXLIB is more suitable.
When NUTTX_NOCXXLIB is select, do not select lower level support.

Change-Id: I158937a4ba02f8fa3c76101acbdfb295d8cd736f
2021-08-26 19:32:24 +08:00
zhuyanlin f2fe51c22d libc:libcxx: add support for libcxxabi.
libcxxabi is either-or select with glibcxx.

Change-Id: I4fbea19f0648ddc318379dd43bac8406f7c86927
2021-08-26 19:32:24 +08:00
zhuyanlin 7f48d13c47 libc:libxx: add new low level c++ standard library support
LLVM libc++abi is a new implementation of low level support for
a standard C++ library.

Change-Id: Ica9c81bd96fd27b169a06e352b0c394d47aed5b6
2021-08-26 19:32:24 +08:00
chao.an bcce3314e5 arch/arm/cortex-m: add up_backtrace support
add up_backtrace support based on push/branch instruction

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 18:31:51 +08:00
chao.an d5d6297ca1 arch/arm/assert: enhance the assert dump
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:31:08 +08:00
chao.an f14bd44001 arch/armv7: add up_backtrace support based on frame pointer
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:30:08 +08:00
buyuer 001eb7786b net/local: Return the partial write size.
Signed-off-by: buyuer <dingddding@163.com>
2021-08-26 13:28:11 +08:00
buyuer 33320329ec vfs: writev should return the partial write size.
Signed-off-by: buyuer <dingddding@163.com>
2021-08-26 13:28:11 +08:00
Kapil Gupta ec99e11f5e esp32/softap: Enable the WPA2 by default to ask user password
Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com>
Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>
2021-08-26 13:26:57 +08:00
ligd f1aec38ffa arm: add ARM_HAVE_NEON to Kconfig
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-08-26 13:25:43 +08:00
Abdelatif Guettouche fc594c5d25 esp32_irq.c: Extend the CPU interrupt/peripheral map to include the
status of the interrupt (enabled/disabled).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 810ed19b8f arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt
Matrix.

This allows manipulating interrupts from both CPUs.  Internal interrupts
however, still need to be disabled/enabled by each CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche a7abd56448 arch/xtensa: Move the Xtensa specific part of interrupts to
xtensa/include/irq.h

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 470799b0b3 arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used
only inside this file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 04cd520293 arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq.
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 237aebb7e1 arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register
address of a peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche 02c17c3169 arch/esp32: Simplify the interrupt allocation process.
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Xiang Xiao d242861c44 libc: Remove the legacy printf support
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-25 12:55:36 -07:00
Abdelatif Guettouche dbdec45049 arch/xtensa/src/common: Use irq_spin APIs in modifyregXX
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 23:32:40 +08:00
YAMAMOTO Takashi 42f1851ca6 tcp_send_buffered.c: Fix snd_wnd
snd_wnd is an offset from the acked sequence number.
2021-08-25 20:56:05 +08:00
YAMAMOTO Takashi 1b82f1c749 tcp_input: snd_wnd processing
* Do not accept the window in old segments.
  Implement SND.WL1/WL2 things in the RFC.

* Do not accept the window in the segment w/o ACK bit set.
  The window is an offset from the ack seq.
  (maybe it's simpler to just drop segments w/o ACK though)

* Subtract snd_wnd by the amount of the ack advancement.
2021-08-25 20:56:05 +08:00
Masayuki Ishikawa af57d04433 Revert "drivers: wireless: Fix ASSERT() in _read_data_len() in gs2200m.c"
We found that the change caused a problem when running a VPN application.
and also confirmed that reverting the commit fixed the issue.

This reverts commit 11a842333f.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-08-25 12:25:39 +08:00
Abdelatif Guettouche 5ff703d5d0 arch/*_testset: Fix few typos.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 00:20:20 +08:00
Masayuki Ishikawa 2b61c8491a boards: lm3s6965-ek: Update qemu-flat/defconfig
Summary:
- Add CONFIG_STACK_COLORATION=y
- Change CONFIG_TASK_NAME_SIZE from 0 to 24
- Add CONFIG_TESTING_OSTEST=y

Impact:
- None

Testing:
- Tested with ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-08-24 12:07:34 +08:00
Masayuki Ishikawa 4413a976eb boards: lm3s6965-ek: Update qemu-protected/defconfig
Summary:
- Add CONFIG_STACK_COLORATION=y
- Change CONFIG_TASK_NAME_SIZE from 0 to 24
- Add CONFIG_TESTING_OSTEST=y

Impact:
- None

Testing:
- Tested with ostest
- NOTE: ostest seems to finish successfully but the victim
  task still exists

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-08-24 12:07:34 +08:00
François Schauber 0bfacf4d12 include/threads.h: add missing semi-colon 2021-08-24 00:14:12 +08:00
Alan C. Assis 6031e06ff2 Move "Contributing" to be after getting started 2021-08-23 21:22:49 +08:00
Alin Jerpelea 07d528fd8d license: Ken Pettit: update licenses to Apache
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-23 11:41:41 +08:00
chao.an 6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-22 14:44:01 +08:00
Abdelatif Guettouche 6c2fcdc45d Documentation: Update ESP32-C3 supported peripheral list.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-21 18:30:53 -03:00
chao.an efaf72a1b1 net/local: correct the return length of sendmsg
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-21 14:59:59 +08:00
chao.an 68d6dbf86f arch/riscv/assert: enhance the assert dump
enhance the assert dump to show the all tasks info including backtrace and registers

[    7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[    7.617000] [ EMERG] riscv_dumpstate: Call Trace:
[    7.617000] [  INFO] [BackTrace| 3|0]:  0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894
[    7.617000] [  INFO] [BackTrace| 3|1]:  0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0
[    7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
...
...
[    7.617000] [ EMERG] riscv_showtasks: Tasks status:
[    7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976
[    7.617000] [  INFO] [BackTrace| 0|0]:  0x4200787e 0x3fc94ff0
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200787e
[    7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
...
[    7.617000] [ EMERG] riscv_taskdump:
[    7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[    7.617000] [  INFO] [BackTrace| 1|0]:  0x420082a6 0x4200328c 0x42001ab4 0x42001a42
[    7.617000] [ EMERG] riscv_registerdump: EPC:420082a6
[    7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
...

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-21 14:58:21 +08:00
chao.an 333191becd riscv/backtrace: add up_backtrace support
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-21 14:56:34 +08:00
Abdelatif Guettouche 2925d4956b xtensa/esp32: Use up_cpu_index instead of this_cpu.
this_cpu requires sched.h to be included.
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche 5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche 56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche 5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted.
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche 97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche 633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts.
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
chao.an c826c37277 nuttx/up_backtrace: add up_backtrace interface
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-20 13:11:45 -03:00
chao.an 904348302a sched/backtrace: simplify the assign of tcb in case of negative pid
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-20 13:11:45 -03:00
Sara Souza e092c457e6 xtensa/lx7: Fix the CROSSDEV variable 2021-08-20 16:48:20 +02:00