The error was introduced by #14393, which was intended to fix this
line for MacOS. This commit makes this line dependent on the host
OS to avoid any compilation errors.
Add support for memory partitioning for OTA updates.
This feature is targeted at the integration of ESP32 boards with RISC-V architecture in conjunction with MCUboot
Signed-off-by: davidiogos <davi.silva@agrosystem.com.br>
fix
CMake Error at boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt:76 (endif):
Flow control statements are not properly nested.
CMake Error at boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt:76 (endif):
Flow control statements are not properly nested.
-- Configuring incomplete, errors occurred!
Not all labels are added because there is no match with the label name.
issue_labeler.yml
os: Linux -> os: linux
001_bug_report.yml
Type: bug -> Type: Bug
Corrected label in links
002_feature_request.yml
Type: enhancement -> Type: Enhancement
Corrected label in links
003_help.yml
Type: question ->Type: Question
Corrected label in links
This PR updates the Build Rules `arch.yml` to build only these Arm32 Targets when we create or update a Complex PR:
- arm-01, arm-03, arm-05, arm-06, arm-07, arm-09, arm-11
No changes for Simple PRs (arm-01 to arm-14) and for Merging PRs (also arm-01 to arm-14).
This will improve our breadth of CI Checks across Arm32 Targets, as explained here: https://github.com/apache/nuttx/issues/14376
nucleo-144 combines 3 different ST boards. This approach is inconsistent with
the support for the rest of the nucleo boards, where each board is in separate folders.
Also nucleo-144 is no longer reserved for STM32F7 chips but other families also use this format.
After this commit nucleo-144 is divided into 3 boards:
- nucleo-f746zg
- nucleo-f767zi
- nucleo-f722ze
This PR creates the new CI Build Jobs `arm64-01` and `x86_64-01`. The new jobs will split and offload the Arm64 and x86_64 Build Targets from `other`. This will reduce our usage of GitHub Runners, to comply with the ASF Policy for GitHub Actions. (Recently we see more PRs for Arm64 and x86_64)
Before the Split: Simple PRs (One Arch and/or One Board) for Arm64 and x86_64 require almost 1 hour for CI Build
- `other` (57 mins): AVR, SPARC, x86, PinePhone, QEMU Arm64, QEMU x86_64
After the Split: Simple PRs for Arm64 and x86_64 will complete under 30 mins
- `other` (24 mins): AVR, SPARC, x86
- `arm64-01` (29 mins): PinePhone, QEMU Arm64
- `x86_64-01` (9 mins): QEMU x86_64
To skip more unnecessary builds: Our Build Rules `arch.yml` shall ignore the label "Area: Documentation", so that a Simple PR + Docs is still a Simple PR. Previously we experienced longer CI Build Times, just because we added docs to our Simple PR. (Now our PR shall be built exactly like a Simple PR)
The updated CI code is explained here: https://github.com/apache/nuttx/issues/13775
* Nucleo-L432KC board was missing internal MCU DAC code.
* DAC is now available on PA4/A3 and /dev/dac0 when enabled.
* Updated info on ADC inputs (PA6/A5,PA7/A6) depending on configuration.
Signed-off-by: Tomasz 'CeDeROM' CEDRO <tomek@cedro.info>
When we submit or update a Complex PR that affects All Architectures (Arm, RISC-V, Xtensa, etc): CI Workflow shall run only half the jobs for RISC-V, Xtensa and Simulator:
- `risc-v-01` to `03`
- `xtensa-01`
- `sim-01`
When the Complex PR is Merged: CI Workflow will still run all jobs for RISC-V, Xtensa and Simulator:
- `risc-v-01` to `06`
- `xtensa-01` to `02`
- `sim-01` to `02`
Simple PRs with One Single Arch / Board will build the same way as before:
- `risc-v-01` to `06`
- `xtensa-01` to `02`
- `sim-01` to `02`
We hope to lower drastically our usage of GitHub Runners before the ASF Deadline, as explained here: https://github.com/apache/nuttx/issues/14376
This commit simplified setitmer implementation by eliminating a redundant conditional branch.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Renamed savedefconfig -> refreshsilent name more consistent with the refresh stage for cmake on github.
Added new savedefconfig to fix
https://github.com/apache/nuttx/issues/14281
Return 0 for CPU ID for any hart ID, and return the current Hart ID for
any CPU ID. At least these values are somewhat usable / meaningful in
non-SMP configurations.
Tiago Medicci Serrano