Commit Graph

53789 Commits

Author SHA1 Message Date
Daniel Jasinski d77ef098c6 build: set CMake policy to allow FetchContent_Populate
FetchContent_Populate is depracated starting from CMake
3.30. Setting this policy to OLD allows clean CMake builds
for configurations that rely on CMake fetch content feature.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-11 03:03:57 +08:00
Alan C. Assis 7e0db94063 arm/lm3s6965-ek: Disable NTPC for lm3s6965 to fix maximum flash space reached 2024-08-10 19:26:32 +08:00
Yanfeng Liu 0a0af89de9 board/lm3s6965-ek: fix memory.ld for PROTECTED
The uflash origin should equal to kflash size, this completes the
fix to unblock CI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-10 19:21:35 +08:00
chenwen@espressif.com cde0de00fe xtensa/esp32s3: Update the rtc code to fix system blocking issue
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
      but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
   2. Corresponding issue link: 89cc9084ab

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-08-09 12:49:34 -03:00
Yanfeng Liu 83932d115b boards/rv-virt: unify rv32 config names
This renames a few RV32 configs to follow the convention that names w/o
numbers are for RV32, so that to be in line with majority RV32 configs.

As a result, we have:  `nsh` vs `nsh64`, `knsh` vs `knsh64`, `pnsh`
vs `pnsh64`,`flats` vs `flats64`, `nsbi` vs `nsbi64`, `libcxx` vs
`libcxx64` etc. This helps us pick the right config name w/o checking
file contents.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:44:40 +08:00
Yanfeng Liu 2afdcfb6a6 boards/lm3s6965-ek: adjust memory.ld to unblock CI
This adjusts memory.ld to unblock CI issue: `nuttx_user.elf
section '.text' will not fit in region 'uflash'`

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu 46f4a24d59 riscv/qemu: add CMake for PROTECTED
This adds CMake support for PROTECTED build mode on rv-virt target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu 34a30e577e riscv/qemu: add CMake for NuttSBI
This allows building NuttSBI based kernel image with CMake so that
to support out-of-tree building.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
chao an 6c97a8f468 sim/login: remove login restrictions to improve the experience for green hands
Most developers start learning Nuttx from sim/nsh, but the login experience is very bad,
they don't know where to get the username and password, this commit will remove the
limitation of sim/nsh login, and add sim/login configuration to ensure the feature of
NSH_CONSOLE_LOGIN is verified.

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-09 11:34:38 -03:00
Saurav Pal 0be6dfb552 fs/mnemofs: Refactor path logic, direntry size bug fix, open free bug fix
Refactoring path logic to prevent logic flaws, direntry size bug fix to allow proper direntry traversal, open free bug fix to prevent memory leak after close.

Signed-off-by: Saurav Pal <resyfer.dev@gmail.com>
2024-08-09 09:00:17 +02:00
Nonpawit Ekburanawat 01bac59cb7 Add STM32H745I-DISCO Per Core Support
- New defconfig for nsh CM4 and CM7
- New linker script for cm4
- Update linker script to include shared memory and condition for flash size
- Update Make and CMake file to compile according to core
- Added UART7 pin by default for CM4 serial output
- Changed userled configuration to fix error

Signed-off-by: Nonpawit Ekburanawat <nonpawit.ek@gmail.com>
2024-08-09 01:58:51 +08:00
Yanfeng Liu bba82bea89 build/cmake: allow gcc-riscv64-unknown-elf for PROTECTED
This allows using Ubuntu stock gcc-riscv64-unknown-elf 10.2
toolchain for PROTECTED build with cmake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 01:58:36 +08:00
Yanfeng Liu 01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu 6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
nuttxs 2af8a886ab arch/xtensa/esp32: Replace nxsig_usleep() with up_udelay() to
avoid context switching, and the actual time difference caused
by the setting of TICK in nxsig_usleep() is quite large.
2024-08-08 20:01:46 +08:00
rongyichang bb29c39d50 drivers/touchscreen: add grab for touchscreen
Providing the capability for applications to exclusively
handle touch events

Signed-off-by: rongyichang <rongyichang@xiaomi.com>
2024-08-08 18:30:32 +08:00
chao an 9cc25523b1 spinlock: add support of spin_trylock_irqsave()
trylock spinlock in critical section:

bool spin_trylock_irqsave(FAR volatile spinlock_t *lock, irqstate_t flags);
bool spin_trylock_irqsave_wo_note(FAR volatile spinlock_t *lock, irqstate_t flags);

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-08 18:26:59 +08:00
Shoukui Zhang a3b94383ed tmpfs: write end of file if open flag with O_APPEND
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-08 17:19:42 +08:00
Shoukui Zhang 3f3ad34f42 Fix greater-than-or-equal-to-zero issue
unsigned_compare: This greater-than-or-equal-to-zero comparison without a signed value is always true. conn->lc_crefs >= 0

Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-08 17:19:42 +08:00
Lup Yuen Lee 3862b71728 risc-v/qemu-rv: Add Build Config for leds64_rust
This PR adds a new Build Config `rv-virt:leds64_rust` that builds the Rust App `leds_rust` for QEMU RISC-V 64-bit. The build requires the [Rust Target `riscv64gc-unknown-none-elf`](https://github.com/apache/nuttx/pull/12858):

```bash
rustup target add riscv64gc-unknown-none-elf
```

New Files:

`boards/risc-v/qemu-rv/rv-virt/configs/leds64_rust/defconfig`: Add new Build Config `rv-virt:leds64_rust`

Updated Docs:

`applications/examples/leds_rust/index.rst`: Add `leds_rust` example app

`platforms/risc-v/qemu-rv/boards/rv-virt/index.rst`: Add `rv-virt:leds64_rust` config
2024-08-08 12:19:25 +08:00
Daniel Jasinski 8399a780d8 build: Fix Toolchain.cmake for CONFIG_SIM_ASAN enabled
This commit adds missing add_link_options to specify sanitizers
also during linking stage.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-08 09:44:47 +08:00
Yanfeng Liu 77cfbf8914 riscv/fork: fix gp register handling
This fixes the handling of gp register in fork.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Yanfeng Liu 3f021d5429 riscv/fork: fix fp/s0 field position
The fp/s0 field position shall be in line with the macro
FORK_FP_OFFSET/FORK_S0_OFFSET.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
zhangshoukui 5df3f5d4f7 Added the documentation about the iic slave driver
Signed-off-by: zhangshoukui <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 75fa94af02 i2c_slave: add poll waiters array
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang f94160095e Adapt i2c slave callback interface for rp2040 and s32k11x
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 4e6f3e9360 I2c slave: Add POLLOUT event for notifie slave write success
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 2093038315 add setup and shutdown for i2c master and slave
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 1ea19e7c54 fix i2c slave register failed
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang f4a234613e Add I2C Slave driver
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 6114c0b948 i2c: Remove useless restrictions
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 2bf13ffbb0 spi: Optimize access to private data
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang a6cea0d82e Restriction declaration spi_slave_unlink function
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang 9ffac12465 spi: Remove useless restrictions
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Lup Yuen Lee 52583fc17e tools/ci: Add Rust Target for QEMU RISC-V 64-bit
This PR updates the Docker Image for NuttX CI, so that it builds Rust Apps correctly for QEMU RISC-V 64-bit. We add the Rust Target for `riscv64gc-unknown-none-elf` to the Docker Image.

In the next PR, we will call the Updated Docker Image to [compile the Rust App `leds_rust`](https://github.com/apache/nuttx/pull/12852), at every run of NuttX CI. This will validate whether Rust Apps are built correctly for QEMU RISC-V 64-bit.

Modified Files:

`tools/ci/docker/linux/Dockerfile`: Add Rust Target `riscv64gc-unknown-none-elf` for Docker CI

`tools/ci/platforms/ubuntu.sh`: Same as above, but for Ubuntu CI

`tools/ci/platforms/msys2.sh`: Same as above, but for MSYS2 CI
2024-08-07 19:59:56 +08:00
zouboan d759611e90 Documentation/platforms:add documentation for Zynq MPSoC and ZCU111
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
2024-08-07 16:21:51 +08:00
YAMAMOTO Takashi d9c90eef13 esp32s3-devkit/toywasm: enable ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK 2024-08-07 15:59:41 +08:00
Lup Yuen Lee 788f91c677 tools/[Rust|D]: Fix the Rust and D Builds for QEMU RISC-V
This PR fixes the build for Rust Apps and D Apps on QEMU RISC-V. Previously the Rust Build selected the [incorrect Rust Target riscv64i-unknown-none-elf](https://lupyuen.github.io/articles/rust5#rust-target-is-incorrect). Now the Rust Build selects the correct Rust Target: riscv64gc-unknown-none-elf.

This PR also fixes the 32-bit RISC-V Target for D Apps. D Targets ("riscv32") are named differently from Rust Targets ("riscv32gc"), this PR restores the correct Target Names.

Note that Rust Apps won't build correctly for QEMU RISC-V 32-bit. This requires a [Rust Custom Target for riscv32gc](https://lupyuen.github.io/articles/rust4#custom-target-for-rust), which will make the NuttX Makefiles much more complicated.

Also note that `hello_d` won't build correctly for 64-bit `rv-virt:nsh64`. To date, NuttX has never supported 64-bit RISC-V for D Apps.

Modified Files:

`tools/Rust.defs`: Rename the RISC-V ISA `imafdc` to `gc` for Rust Targets

`tools/D.defs`: Exclude the RISC-V ISA for D Targets
2024-08-07 10:03:43 +08:00
Ville Juven 9da9d3ea8c binfmt/elf_loadfile: Set sh_addr even if SHF_ALLOC == 0
Set sh_addr for regions that are not allocated. Some relocations might
depend on this.

The fault in my case occurs when setting CONFIG_HAVE_CXX=y. In this case,
the .ctor and .dtor sections do not get allocated, but the crt code
depends on linker defined symbols _sctors/_ectors etc. These generate PC
relative relocations and thus, the .ctor and .dtor output sections need
an output VMA even though nothing is there. Otherwise the relocations will
point to god knows where (in my case to address 0).

The problem results in full system crash later:
elf_symvalue: Other: 00000000+00000001=00000001
up_relocateadd: PCREL_HI20 at c00002dc [00000417] to sym=0x80409e80 st_value=1
_calc_imm: offset=-3221226203: hi=-786432 lo=-731
up_relocateadd: ERROR: PCREL_HI20 at c00002dc bad:ffffffff40000000
elf_relocateadd: ERROR: Section 2 reloc 52: Relocation failed: -22

The RISC-V elf64 linker does not like the uninitialized PC relative
relocation entries, as the relocation offset cannot be reached with
with the RV64 instruction set.

More about this issue can be found here:
https://github.com/apache/nuttx/pull/11322
2024-08-07 08:45:50 +08:00
Daniel Jasinski a09867df8c build: Fix libc/pwd CMakeLists.txt
This commit fixes erronous assignment of lib_pwd_globals.c
previously guarded by CONFIG_LIBC_PASSWD_FILE. Original
Make.defs file has this in CSRCS scope.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-07 08:45:19 +08:00
Ville Juven 2eb26d04f4 rv-virt/pnsh: Refresh PROTECTED mode configs 2024-08-07 02:41:14 +08:00
Ville Juven 622e5b26b3 riscv/syscall: Fix fork() system call
When executing fork() via a system call, the parent's stack gets corrupted
by the child, as during exception return the child loads the parent's
stack pointer from the context save area.

This happens because the full parent stack (including what has been pushed
during the system call) is copied to the child. What should be copied, is
only the user stack of the parent (the kernel stack is not interesting).

Fix this by only copying the parent's user stack to the child; and make
the child return directly to userspace (not via dispatch_syscall).
2024-08-07 02:41:14 +08:00
Ville Juven 2cf8ac2f63 risc-v/riscv_swint.c: Simplify implementation of dispatch_syscall
Simplifies the implementation of dispatch_syscall, making it easier to
understand and maintain. Let the C-compiler do most of the work, instead
of doing everything as inline assembly.
2024-08-07 02:41:14 +08:00
Ville Juven fa71bc3d74 riscv/syscall: Add dependency to RISCV_PERCPU_SCRATCH when LIB_SYSCALL=y
The per CPU scratch register is needed by system calls -> enable it by
default.
2024-08-07 02:41:14 +08:00
Julian Oes 75c65c7ce9 arch/stm32h7: add defines for USART clock selection
This adds the necessary defines to set the USARTs' kernel clock source
selection.

This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.

This is according to the reference manual RM0399 page 448.
2024-08-06 14:31:21 +08:00
simbit18 439b9e9683 ISSUE_TEMPLATE: Fixed incorrect links for issue forms
Correct links:

- Bug report

- Feature request

- General Help

add BSD keyword
2024-08-05 15:35:48 -03:00
Filipe Cavalcanti 65e989e063 arch/risc-v: add support for motor control on ESP32|C6|H2 2024-08-05 15:35:19 -03:00
Rodrigo Sim fddebc267d arm/stm32f401rc-rs485: Add support to RFID MFRC522
Signed-off-by: Rodrigo Sim rcsim10@gmail.com
2024-08-05 11:03:29 -03:00
Yanfeng Liu a36c168e54 riscv/nsbi: fix up_udelay for rv32
This fixes riscv_sbi_get_time for rv32 and NuttSBI is used.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-05 16:21:49 +08:00
chao an 4ef3eeb305 arch/x86_64: fix build break if disable CONFIG_SPINLOCK
Create version.h
chip/intel64_irq.c:78:34: error: conflicting type qualifiers for ‘g_irq_spin’
   78 | static spinlock_t                g_irq_spin;
      |                                  ^~~~~~~~~~
In file included from chip/intel64_irq.c:40:
include/nuttx/spinlock.h:168:28: note: previous declaration of ‘g_irq_spin’ with type ‘spinlock_t’ {aka ‘volatile unsigned char’}
  168 | extern volatile spinlock_t g_irq_spin;
      |                            ^~~~~~~~~~
chip/intel64_cpu.c: In function ‘x86_64_cpu_ready_set’:
chip/intel64_cpu.c:314:3: warning: implicit declaration of function ‘spin_lock’ [-Wimplicit-function-declaration]
  314 |   spin_lock(&g_ap_boot);
      |   ^~~~~~~~~
chip/intel64_cpu.c:322:3: warning: implicit declaration of function ‘spin_unlock’; did you mean ‘sched_unlock’? [-Wimplicit-function-declaration]
  322 |   spin_unlock(&g_ap_boot);
      |   ^~~~~~~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-05 16:20:47 +08:00