when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This provides a capable bootloader that may be run from OCRAM.
The OCRAM contains regions that are always zero, so the linker
file avoids those with best effort.
iMX9 infrastructure expects:
- 0x20480000 (Start of OCRAM, AHAB)
- 0x2049a000 (NuttX or SPL)
- 0x204e0000 (ARM Trustzone, not used)
When started from SD-card, the offsets are:
- 0x1f000 with AHAB
- 0xa000 without AHAB
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Value 1021, when read from ICC_IAR0_EL1 means:
"The GIC returns this value in response to a read of ICC_IAR0_EL1 or ICC_HPPIR0_EL1 at EL3,
to indicate that the interrupt being acknowledged is one which is expected to be handled at
Non-secure EL1 or EL2. This INTID is only returned when the PE is executing at EL3 using
AArch64 state, or when the PE is executing in AArch32 state in Monitor mode."
When this happens:
- FIQ is fired on group0
- IRQ is pending at group1
So simply check and handle the interrupt. In short, this provides interrupt support for
EL3.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This provides means to run NuttX completely in EL3. This may
be useful with NuttX based bootloaders that are executed from
OCRAM. Instead of SPL/U-boot combo, NuttX may replace SPL
completely.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
We can save execution time by
inline arm64_fullcontextrestore and arm64_switchcontext
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Optimal size of granule is 64B (the dcache line size).
We can use it now as we don't have max. 32 granules limitation anymore.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Using user allocated buffers for DMA transfers is not safe for two reasons:
- User space memory is virtual memory, DMA needs physical memory
- User memory buffer alignment cannot be guaranteed -> cache line ops
are not safe
Add a simple allocator for DMA safe memory. It will provide contiguous
blocks of memory with D-Cache line size alignment.
NOTE: The optimal granule size is the D-Cache line size (64), but due
to restrictions in the granule allocator this would result in a maximum
block size of 2K only, thus use 256B granules instead givin 8K max block
size.
Once the granule allocator is fixed this limitation can be removed.
This patch adds a way to configure PLL frequencies. The configuration is
given by board logic.
These values should only be modified by the bootloader, but we don't have
that yet so the flag is never activated.
The frequency LUT idea is not necessary as the PLL output can be calculated
by the CPU. It is better to do this as the clocks are set by the SPL (2nd
stage program loader) which means the NuttX payload would not have access
to such a LUT anyhow.
The mask PLL_DIV_RDIV_MASK is also fixed, as that was simply wrong.
Also add call to imx9_clockconfig (although it does not do anything yet).
This driver supports both eDMA3 and eDMA4 (also referred to as DMA0 / DMA1
in some contexts..)
The IP blocks are almost identical, with sufficiently minor differences
to use them via a unified driver. The price is a great amount of code
obfuscation in the hardware description layer.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.
flat and protected mode should be the same as before.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.
So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.
The driver uses source 0, and leaves source 1 disabled.
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module
Signed-off-by: W-M-R <mike_0528@163.com>
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.
This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.
For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.
This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Jouni Ukkonen