Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.
Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
For datagram unix sockets, the `SO_SNDBUF` value imposes an upper limit on the size of outgoing datagrams.
Note: We don't support to change the buffer size yet, so only add support to getsockopt now.
Refs: https://man7.org/linux/man-pages/man7/unix.7.html
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
When tun_txavail_work is running, switch to tun_close thread and priv->lock will be destroyed, then switch back to tun_txavail_work thread, an error will occur when nxmutex_unlock(&priv->lock)
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
When ESP32's BLE is enabled, select the option to pin the HCI TX
thread to a specific core. This is necessary to avoid problems
with the BLE task that runs pinned to the PRO CPU (core 0) while
running with SMP enabled.
By enabling the config `CONFIG_BLUETOOTH_TXCMD_PINNED_TO_CORE` and
setting the value of `CONFIG_BLUETOOTH_TXCMD_CORE`, it's possible
to pin the HCI TX thread to a specific core on a SMP-enabled setup.
This is necessary for devices that require that the function that
sends data (`bt_send`) to be called from a specific core.
1. Both IPv6 addresses and net masks should be stored in network byte
order
2. Fix last 2 bytes of mask applying (although it seldom triggers)
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
__dtoa is not used because currently NuttX uses other
function called __dtoa_engine() to do the same thing
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
and size must be power-of-two aligned with base
This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
chao an