with other functionalities removed.
reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs
before
text data bss dec hex filename
178368 876 130604 309848 4ba58 nuttx
after
text data bss dec hex filename
178120 876 130212 309208 4b7d8 nuttx
szie change -248
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit fixes the regression from https://github.com/apache/nuttx/pull/13561
In order to determine whether a context switch has occurred,
we can use g_running_task to store the current regs.
This allows us to compare the current register state with the previously
stored state to identify if a context switch has taken place.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
We need to record the parent's integer register context upon exception
entry to a separate non-volatile area. Why?
Because xcp.regs can move due to a context switch within the fork() system
call, be it either via interrupt or a synchronization point.
Fix this by adding a "sregs" area where the saved user context is placed.
The critical section within fork() is also unnecessary.
There was an error in the fork() routine when system calls are in use:
the child context is saved on the child's user stack, which is incorrect,
the context must be saved on the kernel stack instead.
The result is a full system crash if (when) the child executes on a
different CPU which does not have the same MMU mappings active.
for the citimon stats:
thread 0: thread 1:
enter_critical (t0)
up_switch_context
note suspend thread0 (t1)
thread running
IRQ happen, in ISR:
post thread0
up_switch_context
note resume thread0 (t2)
ISR continue f1
ISR continue f2
...
ISR continue fn
leave_critical (t3)
You will see, the thread 0, critical_section time is:
(t1 - t0) + (t3 - t2)
BUT, this result contains f1 f2 .. fn time spent, it is wrong
to tell user thead0 hold the critical lots of time but actually
not belong to it.
Resolve:
change the nxsched_suspend/resume_scheduler to real hanppends
Signed-off-by: ligd <liguiding1@xiaomi.com>
Summary
The original implement for exception handler is very simple and
haven't framework for breakpoint/watchpoint routine or brk instruction.
I refine the fatal handler and add framework for debug handler to
register or unregister. this is a prepare for watchpoint/breakpoint
implement
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Function `arm64_lowputc` corrupted the x1 register which is used in function `boot_stage_puts`.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
If CONFIG_SMP is not enabled, riscv_cpuindex.c will not be compiled
anyway.
And for CONFIG_ARCH_FPU, if it's not enabled, riscv_fpucmp.c will not
be compiled.
So we can remove the unnecessary macro guard for up_cpu_index() and
up_fpucmp().
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This is actually the same table as entrypoints, so just use the same data, which
can be set before booting any of the harts
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The logical CPU index should be retrieved with this_cpu(); the
riscv_mhartid() returns the actual hart id of the SoC.
For mpfs target for example, NuttX can run on a single HART, for example on mhartid 2, but there is still just one logical CPU for the NuttX.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Because locate the command at the end the resource table is unfriendly
when we want to support multi virtio devices instead only one virtio
rpmsg device.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Add more common command for rptun and rpmsg_virtio frameworks,
also modify the rptun and rpmsg_virtio driver to use the common
commands.
Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
Move the panic logic in common places, later we can move more logic to
the framework instead of having the drivers implement it repeatedly.
Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
add remote addrenv to make the da is start from 0, so the uint32_t
da in resource table can store the correct address
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Previously, address 0x03b70000u was written with shift bits
that only changed the bit width, not the mode. HS mode is
changed via 0x03B90100, which is required, according to Jedec
specs, for DDR mode. HS mode was not applied before. Enforce
DDR mode (50 MHz) for now.
The real boost, however, comes from removing the DMA limitation
at 0x08xxxxxx address space, which now seems unnecessary.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Don't allow unaligned access with the DMA requests.
Return -EFAULT in case the provided address is unaligned.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
sendfifo() function need enable BWR_IE before checking if BWE is enabled
to avoid BWE to be activated between the BWE check and BWR interrupt
enabling, which causes the interrupt to be missed and Data Timeout error.
Set frequency to zero and disable channels in pwm_setup()
to avoid unexpected behaviour when starting PWM.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Filipe Cavalcanti