zhuyanlin
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031c89db89
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power: add PM_IDLE_DOMAIN to pm.h and remove definations
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2022-07-29 11:15:40 +08:00 |
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Xiang Xiao
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c20ed58879
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arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-07-04 13:03:47 +03:00 |
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Xiang Xiao
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3d1ce144df
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arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-07-01 10:44:55 -03:00 |
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Xiang Xiao
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11e1a8b28b
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arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h
follow up the below change:
commit 6357523892
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Mon Nov 1 12:40:51 2021 +0800
arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-06-03 22:25:49 +03:00 |
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chao.an
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3f65b562bb
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arch: inline up_interrupt_context()
inline the up_interrupt_context() to avoid unnecessary stack pushes
Signed-off-by: chao.an <anchao@xiaomi.com>
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2022-05-26 04:36:07 +08:00 |
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chao.an
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5bdfae66ce
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arch/arm: export arm_saveusercontext()
rename arm_saveusercontext() -> up_arm_saveusercontext()
Signed-off-by: chao.an <anchao@xiaomi.com>
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2022-04-18 22:22:16 +08:00 |
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Xiang Xiao
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e923875c1b
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arch/ceva: Remove FAR from chip folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-04-17 18:42:38 +03:00 |
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Xiang Xiao
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b6bc460b2c
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arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-03-14 22:51:00 +02:00 |
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Xiang Xiao
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f94093bc2e
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arch/ceva: Move the idle stack initialization to up_initial_state
to follow other arch's implementation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-03-13 00:28:05 +02:00 |
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Xiang Xiao
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44bd3212d4
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arch: Remove SYS_RESERVED from Kconfg
let's arch define the correct value instead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-27 22:54:13 +08:00 |
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Xiang Xiao
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087b9e5ff3
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arch: Move the content from svcall.h to syscall.h
and remove svcall.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-27 22:54:13 +08:00 |
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Xiang Xiao
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f8df491d5d
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arch/ceva: Update tls handle to the latest mainline
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-02-17 11:06:09 +09:00 |
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ligd
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ee916bdb91
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CEVA: add ceva platform xc5 xm6 support
Signed-off-by: ligd <liguiding1@xiaomi.com>
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2022-01-07 09:31:59 -03:00 |