Squashed commits:
1. Porting prior PCI work in place of jailhouse code
At this point the PCI enumeration works for x86_64 including over
pci-pci bridges.
Running QEMU with this configuration we see the bridge and the
device on the bridge. It also detected the qemu test device
qemu-system-x86_64 \
-cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
--enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -no-reboot \
-device pci-testdev \
-device pci-bridge,id=bridge0,chassis_nr=2 \
-device e1000,bus=bridge0,addr=0x3
qemu_pci_init: Initializing PCI Bus
pci_probe_device: [00:00.0] Found 8086:1237, class/revision 06000002
pci_probe_device: [00:01.1] Found 8086:7010, class/revision 01018000
pci_probe_device: [00:01.2] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.3] Found 8086:7113, class/revision 06800003
pci_probe_device: [00:01.4] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.5] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.6] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.7] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:02.0] Found 1234:1111, class/revision 03000002
pci_probe_device: [00:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:04.0] Found 1b36:0005, class/revision 00ff0000
pci_probe_device: [00:04.0] Probing
pci_check_pci_bridge: [00:05.0] Found Bridge
pci_probe_device: [01:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:05.0] Found 1b36:0001, class/revision 06040000
2. Remove unused CONFIG_PCI_MAX_BDF option
3. Add a workaround for Jailhouse pci scanning
4. Extend BAR parsing and handle PIO and MMIO for pci-testdev
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
5. PCI: Add initial support for QEMU 'edu' test device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
6. Bring up PCI later in boot process
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
7. Add ISR and DMA support to QEMU edu test pci device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
8. Fix bad function prototype definition in qemu_edu
9. intel64: Add a pci test configuration and instructions
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
10. PCI: Fix issue in identification of 64bit bar
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Squashed commits:
1. x86_64: qemu: implement pci-e functions and enumerate pci-e devices on boot
2. virt: add qemu pci-testdev driver
3. pcie: types array should be null terminated
4. pcie: enable don't take flags, hardcoded enabling flags
5. pcie: checking bar > 4 for 64bit bars are sufficient
6. pcie: qemu: remove not used header
7. pcie: qemu: return -EINVAL if buffer argument is NULL
8. pcie: make pcie enumerate routine as common instead of architecture dependent
9. pcie: cosmetic changes to fit check tools
10. pcie: create MSI/MSIX related marcos and simplify the msi/msix routines
* arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer
* arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2
* arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly
* arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling
* arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure
* arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method
* arch: x86_64: Fix C alias of page table and GDT/IST
* arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup
* arch: x86_64: Consolidate MSR definition in arch/arch.h
* arch: x86_64: Edit the way of handling GDT/IST in C into structures
* arch: x86_64: Correct the starting point of isr/irq stack
* arch: x86_64: Update up_initialize.c with the new initializing procedure
* arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT
* arch: x86_64: Overhual of interrupt initialization procedure
* arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory]
* arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure
* arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug
* arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot
* arch: x86_64: Correctly apply license header, comment and format code
* arch: x86_64: properly send a SIGFPE on floating point error
* arch: x86_64: Remove unused variable in up_restore_auxstate
* arch: x86_64: properly trash the processor with an infinite loop
* arch: x86_64: Fix typo in ISR handler causing ISR not handled
* arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path
* arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE
* arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method
* board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support
* arch: x86_64: update defconfigs
* arch: x86_64: rename qemu as qemu-intel64
* arch: x86_64: update Board readme
simbit18