- Edited linker script for shmem to have condition according to cores selected.
- Added new configuration for nsh_cm7_rptun and nsh_cm4_rptun.
- Appended RPTUN bringup code in stm32_bringup.c
Signed-off-by: Nonpawit Ekburanawat <nonpawit.ek@gmail.com>
(1) Keep the `.init_array` and `.ctors` symbols and sort them according to their initialization priority.
(2) Exclude symbols ending with crtend.* and crtbegin.* to support c++
application.if we not exclude crtend.* crtbegin.* frame_dummy will be
added when enable any c++ application with global variables, this symbol
execution is problematic, removing it does not affect the application.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
- New defconfig for nsh CM4 and CM7
- New linker script for cm4
- Update linker script to include shared memory and condition for flash size
- Update Make and CMake file to compile according to core
- Added UART7 pin by default for CM4 serial output
- Changed userled configuration to fix error
Signed-off-by: Nonpawit Ekburanawat <nonpawit.ek@gmail.com>
These configs are changed based on below rules.
1. always enable +CONFIG_LV_USE_NUTTX=y
2. If touchpad is used, enable +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y
3. enable log by +CONFIG_LV_USE_LOG=y
4. If -CONFIG_LV_MEM_CUSTOM=y previously defined, replace it with +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y
5. If -CONFIG_LV_PORT_USE_FBDEV=y, default config is for fbdev. If -CONFIG_LV_PORT_USE_LCDDEV=y, +CONFIG_LV_USE_NUTTX_LCD=y
6. Remove all -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h"
7. If -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y, replace it with CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y. For fbdev, double buffer is automatically detected.
8. If -CONFIG_LV_COLOR_16_SWAP=y, need to upgrade the LCD driver to support hardware byte order swap.
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
Supported external SDRAM (MT48LC4M32B2B5-6AIT:L) on STM32H745I-DISCO dev board.
Though MT48LC4M32B2B5-6AIT:L SDRAM itself provides 32-bit data bus, STM32H745I-DISCO board
routes only DQ[15:0] bits. Thus only half of the memory can be accessed: the accessible memory
configuration is only 1 Meg x 16 x 4 banks instead of 1 Meg x 32 x 4 banks.
Thus the accessible memory size is 8 MBytes.
Testing:
nsh> ramtest -a 0xD0000000 -s 8388608
RAMTest: Marching ones: d0000000 8388608
RAMTest: Marching zeroes: d0000000 8388608
RAMTest: Pattern test: d0000000 8388608 55555555 aaaaaaaa
RAMTest: Pattern test: d0000000 8388608 66666666 99999999
RAMTest: Pattern test: d0000000 8388608 33333333 cccccccc
RAMTest: Address-in-address test: d0000000 8388608
nsh>
Nonpawit Ekburanawat