Commit Graph

88 Commits

Author SHA1 Message Date
chenxiaoyi b6225676f4 xtensa: hostfs: handle nonblock open for iss
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-09-28 13:53:06 +08:00
Tiago Medicci Serrano d6ee1742a9 xtensa/Kconfig: Fix dependency for backtrace dump on Xtensas
`CONFIG_XTENSA_INTBACKTRACE` is necessary to enable backtrace dump
for the tasks because exceptions are treated like interrupts (even
when an exception occurs during a normal task execution). It's now
automatically selected when `CONFIG_SCHED_BACKTRACE` is enabled.
This commit also removes outdated Kconfig options.
2024-09-23 20:40:58 +08:00
chenrun1 8e1a042eef nuttx/atomic.h:Fix missing type declarations at compile time
Summary:
  1.Modify the conditions for entering different include header files
  2.Added pre-definition for _Atomic _Bool when it is missing
  3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
Tiago Medicci Serrano 016bc47a63 esp32s3/elf: Enable ELF loader for ESP32-S3
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
2024-07-31 02:33:12 +08:00
YAMAMOTO Takashi 1ee279c292 nuttx kconfig: rename a few recently-added options
from:
ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_TEXT_HEAP_WORD_ALIGNED_READ

to:
ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ
2024-05-21 01:11:44 +08:00
YAMAMOTO Takashi d196f800b0 Add a few optional text heap APIs to support esp32s3
esp32s3's Internal SRAM 1 and External Memory have two separate mappings
for instructions and data.
2024-05-21 01:11:44 +08:00
Almir Okato d098c1dc87 esp32s3: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.

Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 19:43:05 +08:00
chenwen@espressif.com 62a6a0ab4d xtensa/esp32s3: Tasks use SPIRAM as stack can do SPI flash read/write/erase/map/unmap
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-12-12 22:10:38 -08:00
YAMAMOTO Takashi a59a4ca8ea esp32s3: enable LIBC_ARCH_ATOMIC
Fixes toywasm build.
2023-12-06 21:10:20 +01:00
Eren Terzioglu 438cb4a16a xtensa/esp32s3: Add rtc heap support 2023-11-23 16:49:48 -08:00
Eren Terzioglu 77df430f30 xtensa/esp32s2: Add rtc heap support 2023-11-09 23:58:30 +08:00
chenwen@espressif.com 5239d01dba xtensa/esp32s3: Disable psram as task stack
1. Disable psram as task stack to avoid system blocking.
2. Add some function comments.
2023-11-08 16:25:57 -03:00
hanqiyuan 1a832eb554 xtensa: enable -Oz for xtensa to reduce codesize 2023-08-21 02:58:25 +08:00
Tiago Medicci Serrano 496a77653a arch/xtensa/esp32_esp32s3: prevent arch's libc in the userspace
ESP32 and ESP32-S3 should use the ROM-defined versions of the libc
in flat build and, when building the protected mode, in the kernel.

The ROM-defined version of the libc functions can't be used in the
userspace, however, because it isn't allowed to access the memory
region in flash directly from the userspace. That being said,
`LIBC_PREVENT_STRING_KERNEL` should be selected to avoid building
any implementation of the libc, being the ROM-defined versions
linked instead.

NuttX's software implemented version of the libc will be built in
the userspace. Also, the assembly-defined version of some of the
libc functions (`XTENSA_xxx`) may also be selected to be used in
the userspace.
2023-05-17 13:58:48 +08:00
YAMAMOTO Takashi 0066bf80d2 esp32: enable LIBC_ARCH_ATOMIC
fixes a build issue in https://github.com/apache/nuttx-apps/pull/1723
2023-04-24 10:12:57 +08:00
Gustavo Henrique Nihei 312d6223d3 xtensa: Remove non-supported options from CPUs' specs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-04 12:56:58 +08:00
Gustavo Henrique Nihei 1ecaa4e672 xtensa/esp32s3: Configure the PMS peripheral for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-12-07 03:07:45 +08:00
Gustavo Henrique Nihei bfc40c74d0 xtensa/esp32s3: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-12-07 03:07:45 +08:00
Gustavo Henrique Nihei a5fd1140cb arch/xtensa: Remove non-existent ARCH_HAVE_TESTSET support for ESP32-S2
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-08-27 06:14:57 +02:00
Gustavo Henrique Nihei 60b7479f12 xtensa/esp32: Avoid ROM functions due to error with PIDs 2-7
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei 27fc3c959d xtensa/esp32: Configure the PID controller for privilege separation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei 76acfef5ec xtensa/esp32: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Abdelatif Guettouche 060df22968 arch/xtensa: Initialize the internal heap early.
We might have a situation where an allocation will be requested before
the call to `up_initialize` is performed.  For the current code, this
situation is the stack for the CPUs in SMP mode.

Beside this issue, it's natural to have the internal heap initialized
with the other heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-07 02:32:30 +08:00
zhuyanlin 883337c3a0 xtensa:fpu: add up_fpucmp and enable CONFIG_ARCH_FPU macro
For arch with CP_NUM > 0, enable ARCH_FPU

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-16 12:30:39 +03:00
Gustavo Henrique Nihei c7311829e0 xtensa: Build OS-assisted atomic operations on ESP32-S2
ESP32-S2 lacks support for conditional load/store instructions.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
zhuyanlin d7391bf6bc xtensa: add xtensa arch oneshot ops
As xtensa timer is common in all xtensa chips,
Use oneshot ops, implement a common xtensa oneshot timer.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-28 22:55:00 +08:00
Xiang Xiao 1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
zhuyanlin c833048484 xtensa:kconfig: move ARCH_HAVE_TESTSET config to chip
Some xtensa arch have not implentment testset instructions

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-10 14:22:58 +08:00
Gustavo Henrique Nihei b0d24f53c4 xtensa: Add initial support for ESP32-S3
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
Gustavo Henrique Nihei 73ea0c1627 xtensa: Improve Kconfig description of ESP32-S2 arch family
Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are
composed of a single Xtensa LX7 core.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-07 22:25:05 +01:00
Gustavo Henrique Nihei 78362b0949 xtensa/esp32: Use ROM implementations of libc functions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Petro Karashchenko 51a2db6ffc Kconfig: improve uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Xiang Xiao e30a5f3790 arch/sim: Add new option to enable arch specific hostfs
we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-25 14:42:23 +01:00
zhuyanlin 4db5016d83 arch:hostfs: add cache coherence config for semihosting option
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
Abdelatif Guettouche 6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
zhuyanlin cf1a04d0a2 xtensa:cache: add lock & unlock feature
Since some xtensa cores cache support lock & unlock feature.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-10-22 13:31:32 -03:00
Xiang Xiao 91398e73eb arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-10-19 00:33:51 +02:00
Gustavo Henrique Nihei a5f9e29d78 xtensa/esp32s2: Enable support for "make bootloader" target
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei c23986ec63 xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-24 10:48:19 -07:00
zhuyanlin d6fe0f18f5 arch:xtensa: add XTENSA_CACHE config support
Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE
2021-09-07 13:33:31 +08:00
zhuyanlin 355133f218 arch:xtensa: add new GNU toolchain for xtensa.
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
2021-08-04 18:16:14 +02:00
jordi f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
2021-07-23 02:32:19 -07:00
Abdelatif Guettouche af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 07:14:17 -05:00
Alan C. Assis 7767acd24a Add initial ESP32S2 Xtensa support 2021-06-01 07:49:54 +02:00
Abdelatif Guettouche cc23bdeca4 boards/xtensa/esp32: Add a section in external memory to hold some BSS
data.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-23 16:39:01 +09:00
Abdelatif Guettouche a68a39c785 xtensa/esp32: Move internal heap to the beginning of region 2.
Internal heap was occupying the region straight after .data up to
HEAP_REGION1.  The issue with this is if static allocation is large,
we'll end up with too little memory left for the internal heap.
Moving it to the beginning of region 2 gives us more room to play with.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
chenwen 19627095e4 esp32/esp32_allocateheap.c: Support the maximum available internal heap configuration 2021-03-02 18:27:20 -08:00
YAMAMOTO Takashi aed24f1255 esp32: Retire XTENSA_IMEM_PROCFS
Now /proc/meminfo has the equivalent.
2021-02-12 03:16:03 -08:00
Abdelatif Guettouche 6bc070024d arch/xtensa/Kconfig: Reduce the default value of the internal memory.
The static memory is now divided at almost the middle to not override
the ROM data.  The old 0x28000 will take all of what's left for heap
region1.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-27 09:49:58 -08:00
Abdelatif Guettouche c00141c41a arch/xtensa/Kconfig: The ESP32 has a different numbers for vectors and
IRQs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-15 09:47:33 +01:00