Change the qmeu pci test code for new pci driver framework
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
If libcxxabi is not enabled, the toolchain default implementation will be used. However, arm-gcc does not enable thread
support by default, which will cause errors in a multi-threaded environment.
libcxx depends on pthread_key_create
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
In the following code, even though the application does not use exceptions, an exception is still thrown in libcxx
If libcxxabi is not enabled, the toolchain default implementation will be used. However, arm-gcc does not enable thread
support by default, which will cause errors in a multi-threaded environment.
Therefore, we need to use libcxxabi to ensure normal functions in a multi-threaded environment.
using namespace std;
void foo(bool recur);
int bar(bool recur)
{
if (recur) {
foo(false);
}
return 0xFAFAFA;
}
void foo(bool recur)
{
static int i = bar(recur);
cout << "Static is:" << i << "\n";
}
int main(int argc, char *argv[])
{
foo(true);
return 0;
}
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Since pthread_mutex is implemented by sem, it is impossible to see in ps who holds the lock and causes the wait.
Replace sem with mutex implementation to solve the above problems
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Make umm & kmm heap alloc more clear, and possible support FLAT build to
enable kernel heap.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
reason:
spin_initialize is often used to release a lock,
and if we don't include a memory barrier,
it may lead to the lock being released prematurely.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. correct the armv8-r fpu flag from vfpv3-d16 to fpv5-sp-d16
2. add neon support
This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.
Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.
Reference:
https://developer.arm.com/Processors/Cortex-R52
Instruction set:
Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point
Unit either with single-precision or double precision and Neon.
Signed-off-by: chao an <anchao@lixiang.com>
reason:
Since smp call handler may lead to context switching,
we need to update the context information by calling up_cpu_paused_[save|restore].
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Normally ccache places the temporary files in `~/.ccache`, when invoking the container with
`-u <uid>:<gid>`
as e.g. Jenkins does, this might result in a invalid/unknown home folder.
Thus ccache tries to write to `/.ccache` which doesn't exist and the user doesn't have any permissions.
Explicitly set `CCACHE_DIR` to a folder with appropriate permissions.
reason:
dynaminc create g_irqmap to reduce the use of data segments
CONFIG_ARCH_NUSER_INTERRUPTS should be one more than the number of IRQs actually used
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
lipengfei28