Commit Graph

14 Commits

Author SHA1 Message Date
yezhonghui f81c844685 arm64 support gicv2m for pci irq
Signed-off-by: yezhonghui <yezhonghui@xiaomi.com>
2024-09-28 16:09:11 +08:00
Bowen Wang bf5c571098 arm64/qemu_boot: add arm64 pci io memory map
and rename other pci region name to make them more
readable

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang b12fa7f760 qemu_boot: change IVSHMEM memory region to PCI memory region
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang 99876fa529 arm64/mmu_region: add ivshmem mmu region for arm64
Now the ivhsmem memory region can be used in arm64

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
yangshuyong 6a09037efd arm64/qemu_boot: add the pcie cfg address for arm64
1. Extend the arm64 address to 48bit;
2. Add pci cfg address to the mmu map table;

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
2024-09-10 14:34:31 +08:00
hujun5 13bbea0f1c arm64: inline up_cpu_index
reduce the time consumed by function call

test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-06-28 21:29:33 +08:00
wangming9 4422c26c78 arch/arm64: Change the ARM configuration to ARM64.Add ARM64_NEON configuration
Summary:
1. Change the ARM to ARM64
2. Add CONFIG_ARM64_NEON

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-06-20 09:41:28 +08:00
Xiang Xiao ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
zhangyuan21 dc55205ee5 arch/arm64: get_cpu_id according to the correct affinity level
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
zhangyuan21 f8b5fd2a9a arch/arm64: send sgi with correct aff and target list
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-21 09:58:34 -03:00
qinwei1 518eb4076e arm64: ARMv8-r(Cortex-R82) support(mpid fix)
Summary
  Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
Lee Lup Yuen 6aba739f05 arch/arm64: Add support for Generic Interrupt Controller Version 2
Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.

This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).

-   `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.

-   `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).

    Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.

-   `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.

-   `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.

-   `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.

-   `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.

-   `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.

-   `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
2022-11-20 21:44:12 -08:00
Hidenori Matsubayashi 06cf41901f arch/arm64: cleanup defconfigs
Use CONFIG_ARCH_CHIP_QEMU instead of CONFIG_ARCH_CHIP_QEMU_A53. This is because these configurations depend on the hardware configuration of qemu (memory map, irq numbers, etc.).

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-13 19:26:26 +08:00
qinwei1 e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00