Commit Graph

12 Commits

Author SHA1 Message Date
Xiang Xiao c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Huang Qi 8532feda78 arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Masayuki Ishikawa bb255d075c arch: risc-v: Author Masayuki Ishikawa: Update license to Apache
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-12 16:15:44 +08:00
Xiang Xiao 92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:27:13 -08:00
Xiang Xiao fe8122ee2b arch/risc-v: Remove duplicated declaration for up_irq_save and up_irq_restore
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-19 08:29:42 +09:00
Xiang Xiao cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Xiang Xiao 68951e8d72 Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
Masayuki Ishikawa d76ba14d58 arch: fe310: Fix mstatus handling
In previous commit, mstatus.mie was set when creating a new task
    but this change was incorrect and had a side effect such that
    a machine interrupt would be enabled just before returning from
    interrupt handling routine to switch context.

    Also, mstatus.mpp is set to machine mode in up_get_newintctx()
    instead of fe310_dispatch_irq().
2020-01-08 10:39:00 -03:00
Masayuki Ishikawa 4ea49c5691 Fix issues on fe310 including interrupt handling (#46)
* arch: fe310: Fix comments

* arch: fe310: Improve irq handling in fe310_serial.c

* arch: fe310: Fix initial interrupt status (mstatus)

Also, removed unnecessary up_enable_irq(FE310_IRQ_ECALLM)
2020-01-07 07:17:39 -03:00
Masayuki Ishikawa 466ab56c10 Merged in masayuki2009/nuttx.nuttx/fe310_gpio (pull request #1097)
fe310 gpio

* arch: risc-v: Add arch/risc-v/src/common/up_mdelay.c

* arch: risc-v: Add arch/risc-v/src/common/up_udelay.c

* arch: fe310: Add #include <stdint.h> to fe310_start.c

* arch: risc-v: Add up_ack_irq() definition to commpn/up_internal.h

* arch: fe310: Add FE310 GPIO driver

* boards: hifive-revb: Add compiler optimization

* boards: hifive1-revb: Add auto leds related files.

* arch: fe310: Add CPU activity led to fe310_idle.c

* boards: hifive-revb: Add a button

    NOTE: still having a trouble in signal handling.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-12-19 04:59:30 +00:00
Masayuki Ishikawa 2cde7dcc8d Merged in masayuki2009/nuttx.nuttx/sparkfun_redv (pull request #1091)
Sparkfun RED-V Things Plus

* board: hifive1-revb: Update README-qemu.txt

* arch: fe310: Works with SparkFun RED-V Things Plus

    Should work with HiFive1 Rev.B but not tested yet.

* boards: hifive1-revb: Works with SparkFun RED-V Things Plus

    Should work with HiFive1 Rev.B but not tested yet.

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-12-08 12:42:48 +00:00
Masayuki Ishikawa 7a8e9581ca Merged in masayuki2009/nuttx.nuttx/hifive1-qemu (pull request #1078)
HiFive1 with qemu

* arch: risc-v: Add include/.gitignore

* arch: risc-v: Add src/.gitignore

* arch: risc-v: Remove uncommon function prototypes in include/irq.h

* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h

* arch: risc-v: Add src/common/up_modifyreg32.c

* arch: risc-v: Enable include Make.dep in src/Makefile

* arch: risc-v: Fix stack coloration in common/up_createstack.c

* arch: risc-v: Add common/up_puts.c

* arch: risc-v: Add common/up_checkstack.c

* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c

    This change is same as other architectures like arm/src/armv7-m

* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig

* arch: risc-v: Add SiFive fe310 processor

    NOTE: Currently only tested with qemu

* boards: hifive1-revb: Add SiFive hifive1-revb board

    NOTE: Currently only tested with qemu

* tools: Add fe310 processor to configure.sh

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-11-28 20:37:24 +00:00