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stm32_eth: Busy bit is cleared before accessing the MACMIIAR register.

This commit is contained in:
Fotis Panagiotopoulos 2023-02-16 21:33:01 +02:00 committed by Xiang Xiao
parent de01550e7e
commit f78bdd3978
1 changed files with 17 additions and 5 deletions
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22
arch/arm/src/stm32/stm32_eth.c
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@ -2853,15 +2853,21 @@ static int stm32_phyread(uint16_t phydevaddr,
volatile uint32_t timeout;
uint32_t regval;
regval = stm32_getreg(STM32_ETH_MACMIIAR);
/* Clear the busy bit before accessing the MACMIIAR register. */
regval &= ~ETH_MACMIIAR_MB;
stm32_putreg(regval, STM32_ETH_MACMIIAR);
/* Configure the MACMIIAR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = stm32_getreg(STM32_ETH_MACMIIAR);
regval &= ETH_MACMIIAR_CR_MASK;
/* Set the PHY device address, PHY register address, and set the buy bit.
* the ETH_MACMIIAR_MW is clear, indicating a read operation.
/* Set the PHY device address, PHY register address, and set the busy bit.
* the ETH_MACMIIAR_MW is clear, indicating a read operation.
*/
regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK;
@ -2912,15 +2918,21 @@ static int stm32_phywrite(uint16_t phydevaddr,
volatile uint32_t timeout;
uint32_t regval;
regval = stm32_getreg(STM32_ETH_MACMIIAR);
/* Clear the busy bit before accessing the MACMIIAR register. */
regval &= ~ETH_MACMIIAR_MB;
stm32_putreg(regval, STM32_ETH_MACMIIAR);
/* Configure the MACMIIAR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = stm32_getreg(STM32_ETH_MACMIIAR);
regval &= ETH_MACMIIAR_CR_MASK;
/* Set the PHY device address, PHY register address, and set the busy bit.
* the ETH_MACMIIAR_MW is set, indicating a write operation.
* the ETH_MACMIIAR_MW is set, indicating a write operation.
*/
regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK;