Fix LPC17 CAN driver; TX must be interrupt driven
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4290 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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d6979d7594
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@ -203,6 +203,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable);
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static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg);
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static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id);
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static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg);
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static bool can_txready(FAR struct can_dev_s *dev);
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static bool can_txempty(FAR struct can_dev_s *dev);
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/* CAN interrupts */
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@ -228,6 +229,7 @@ static const struct can_ops_s g_canops =
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.co_ioctl = can_ioctl,
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.co_remoterequest = can_remoterequest,
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.co_send = can_send,
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.co_txready = can_txready,
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.co_txempty = can_txempty,
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};
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@ -739,6 +741,19 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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regval = can_getreg(priv, LPC17_CAN_SR_OFFSET);
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if ((regval & CAN_SR_TBS1) != 0)
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{
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/* Make sure that buffer 1 TX interrupts are enabled BEFORE sending the
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* message. The TX interrupt is generated when the TBSn bit in CANxSR
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* goes from 0 to 1 when the TIEn bit in CANxIER is 1. If we don't
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* enable it now, we may miss the TIE1 interrupt.
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*
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* NOTE: The IER is also modified from the interrupt handler, but the
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* following is safe because interrupts are disabled here.
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*/
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval |= CAN_IER_TIE1;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Set up the transfer */
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can_putreg(priv, LPC17_CAN_TFI1_OFFSET, tfi);
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@ -753,16 +768,23 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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#else
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can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_TR);
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#endif
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/* Tell the caller that the transfer is done. It isn't, but we have
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* more transmit buffers and this can speed things up.
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*/
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can_txdone(dev);
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}
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else if ((regval & CAN_SR_TBS2) != 0)
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{
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/* Set up the transfer */
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/* Make sure that buffer 2 TX interrupts are enabled BEFORE sending the
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* message. The TX interrupt is generated when the TBSn bit in CANxSR
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* goes from 0 to 1 when the TIEn bit in CANxIER is 1. If we don't
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* enable it now, we may miss the TIE2 interrupt.
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*
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* NOTE: The IER is also modified from the interrupt handler, but the
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* following is safe because interrupts are disabled here.
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*/
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval |= CAN_IER_TIE2;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Set up the transfer */
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can_putreg(priv, LPC17_CAN_TFI2_OFFSET, tfi);
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can_putreg(priv, LPC17_CAN_TID2_OFFSET, tid);
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@ -776,29 +798,20 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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#else
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can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_TR);
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#endif
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/* Tell the caller that the transfer is done. It isn't, but we have
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* more transmit buffers and this can speed things up.
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*/
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can_txdone(dev);
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}
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else if ((regval & CAN_SR_TBS3) != 0)
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{
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/* We have no more buffers. We will make the caller wait. First, make
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* sure that all buffer 3 interrupts are enabled BEFORE sending the
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* message. The TX interrupt is generated TBSn bit in CANxSR goes from 0
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* to 1 when the TIEn bit in CANxIER is 1. If we don't enable it now,
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* we will miss the TIE3 interrupt. We enable ALL TIE interrupts here
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* because we don't care which one finishes: When first one finishes it
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* means that a transmit buffer is again available.
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/* Make sure that buffer 3 TX interrupts are enabled BEFORE sending the
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* message. The TX interrupt is generated when the TBSn bit in CANxSR
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* goes from 0 to 1 when the TIEn bit in CANxIER is 1. If we don't
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* enable it now, we may miss the TIE3 interrupt.
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*
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* NOTE: The IER is also modified from the interrupt handler, but the
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* following is safe because interrupts are disabled here.
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*/
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval |= (CAN_IER_TIE1 | CAN_IER_TIE2 | CAN_IER_TIE3);
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regval |= CAN_IER_TIE3;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Set up the transfer */
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@ -826,6 +839,27 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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return ret;
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}
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/****************************************************************************
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* Name: can_txready
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*
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* Description:
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* Return true if the CAN hardware can accept another TX message.
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*
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* Input Parameters:
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* dev - An instance of the "upper half" can driver state structure.
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*
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* Returned Value:
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* True is the CAN hardware is ready to accept another TX message.
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*
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****************************************************************************/
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static bool can_txready(FAR struct can_dev_s *dev)
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{
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FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv;
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uint32_t regval = can_getreg(priv, LPC17_CAN_SR_OFFSET);
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return ((regval & (CAN_SR_TBS1 | CAN_SR_TBS2 | CAN_SR_TBS3)) != 0);
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}
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/****************************************************************************
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* Name: can_txempty
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*
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@ -840,7 +874,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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* dev - An instance of the "upper half" can driver state structure.
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*
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* Returned Value:
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* Zero on success; a negated errno on failure
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* True is there are no pending TX transfers in the CAN hardware.
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*
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****************************************************************************/
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@ -907,16 +941,44 @@ static void can_interrupt(FAR struct can_dev_s *dev)
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can_receive(dev, hdr, (uint8_t *)data);
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}
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/* Check for a transmit interrupt from buffer 1, 2, or 3 meaning that at
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* least one TX is complete and that at least one TX buffer is available.
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*/
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/* Check for TX buffer 1 complete */
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if ((regval & (CAN_ICR_TI1 | CAN_ICR_TI2 |CAN_ICR_TI3)) != 0)
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if ((regval & CAN_ICR_TI1) != 0)
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{
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/* Disable all further TX interrupts */
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/* Disable all further TX buffer 1 interrupts */
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval &= ~CAN_IER_TIE1;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Indicate that the TX is done and a new TX buffer is available */
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can_txdone(dev);
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}
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/* Check for TX buffer 2 complete */
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if ((regval & CAN_ICR_TI2) != 0)
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{
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/* Disable all further TX buffer 2 interrupts */
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval &= ~CAN_IER_TIE2;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Indicate that the TX is done and a new TX buffer is available */
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can_txdone(dev);
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}
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/* Check for TX buffer 3 complete */
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if ((regval & CAN_ICR_TI3) != 0)
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{
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/* Disable all further TX buffer 3 interrupts */
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regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
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regval &= ~(CAN_IER_TIE1 | CAN_IER_TIE2 | CAN_IER_TIE3);
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regval &= ~CAN_IER_TIE3;
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can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
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/* Indicate that the TX is done and a new TX buffer is available */
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@ -349,13 +349,13 @@ CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=100
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# PWM configuration
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#
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# The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
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# a pulse train using several options (see board.h). Here the default setup is for TIM1, CH1.
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# Don't forget to enable CONFIG_STM32_TIM1
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# a pulse train using several options (see board.h). Here the default setup is for TIM4, CH2.
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# Don't forget to enable CONFIG_STM32_TIM4
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#
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CONFIG_PWM=n
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CONFIG_PWM_PULSECOUNT=y
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CONFIG_STM32_TIM1_PWM=y
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CONFIG_STM32_TIM1_CHANNEL=1
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CONFIG_PWM_PULSECOUNT=n
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CONFIG_STM32_TIM4_PWM=y
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CONFIG_STM32_TIM4_CHANNEL=2
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#
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# General build options
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@ -375,9 +375,11 @@ static int can_xmit(FAR struct can_dev_s *dev)
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canllvdbg("xmit head: %d tail: %d\n", dev->cd_xmit.cf_head, dev->cd_xmit.cf_tail);
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/* Check if the xmit FIFO is empty */
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/* Check if the xmit FIFO is not empty and the CAN hardware is ready to accept
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* more data.
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*/
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if (dev->cd_xmit.cf_head != dev->cd_xmit.cf_tail)
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if (dev->cd_xmit.cf_head != dev->cd_xmit.cf_tail && dev_txready(dev))
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{
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/* Send the next message at the head of the FIFO */
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@ -401,7 +403,7 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t
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FAR struct can_dev_s *dev = inode->i_private;
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FAR struct can_fifo_s *fifo = &dev->cd_xmit;
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FAR struct can_msg_s *msg;
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bool empty = false;
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bool inactive;
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ssize_t nsent = 0;
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irqstate_t flags;
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int nexttail;
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@ -414,11 +416,12 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t
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flags = irqsave();
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/* Check if the TX FIFO was empty when we started. That is a clue that we have
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* to kick off a new TX sequence.
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/* Check if the TX is inactive when we started. In certain race conditionas, there
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* may be a pending interrupt to kick things back off, but we will here that there
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* is not. That the hardware is IDLE and will need to be kick-started.
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*/
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empty = (fifo->cf_head == fifo->cf_tail);
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inactive = dev_txempty(dev);
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/* Add the messages to the FIFO. Ignore any trailing messages that are
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* shorter than the minimum.
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@ -455,11 +458,12 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t
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goto return_with_irqdisabled;
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}
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/* If the FIFO was empty when we started, then we will have
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* start the XMIT sequence to clear the FIFO.
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/* If the TX hardware was inactive when we started, then we will have
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* start the XMIT sequence generate the TX done interrrupts needed
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* to clear the FIFO.
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*/
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if (empty)
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if (inactive)
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{
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can_xmit(dev);
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}
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@ -483,7 +487,7 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t
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/* Re-check the FIFO state */
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empty = (fifo->cf_head == fifo->cf_tail);
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inactive = dev_txempty(dev);
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}
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/* We get here if there is space at the end of the FIFO. Add the new
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@ -507,7 +511,7 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer, size_t
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* we need to kick of the XMIT sequence.
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*/
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if (empty)
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if (inactive)
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{
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can_xmit(dev);
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}
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@ -1,7 +1,7 @@
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/************************************************************************************
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* include/nuttx/can.h
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*
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* Copyright (C) 2008, 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2008, 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -84,6 +84,7 @@
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#define dev_ioctl(dev,cmd,arg) dev->cd_ops->co_ioctl(dev,cmd,arg)
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#define dev_remoterequest(dev,id) dev->cd_ops->co_remoterequest(dev,id)
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#define dev_send(dev,m) dev->cd_ops->co_send(dev,m)
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#define dev_txready(dev) dev->cd_ops->co_txready(dev)
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#define dev_txempty(dev) dev->cd_ops->co_txempty(dev)
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/* CAN message support */
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@ -205,6 +206,10 @@ struct can_ops_s
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CODE int (*co_send)(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg);
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/* Return true if the CAN hardware can accept another TX message. */
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CODE bool (*co_txready)(FAR struct can_dev_s *dev);
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/* Return true if all message have been sent. If for example, the CAN
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* hardware implements FIFOs, then this would mean the transmit FIFO is
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* empty. This method is called when the driver needs to make sure that
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