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arch/stm32f3: fix ADC clock after ef517ed

This commit is contained in:
raiden00pl 2022-11-17 10:39:23 +01:00 committed by Xiang Xiao
parent b239985037
commit f22ef83cd6
2 changed files with 44 additions and 0 deletions
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27
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@ -52,6 +52,15 @@
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/* Max ADC clock frequency is 72MHz */
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
# if STM32_PLL_FREQUENCY > 72000000
# error ADCxxPRES is hardcoded to 1 - PLL frequency is too high
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -555,6 +564,24 @@ static void stm32_stdclockconfig(void)
stm32_rcc_enablelse();
#endif
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
/* Configure ADC12 clock */
regval = getreg32(STM32_RCC_CFGR2);
regval &= ~RCC_CFGR2_ADC12PRES_MASK;
regval |= RCC_CFGR2_ADC12PRESd1;
putreg32(regval, STM32_RCC_CFGR2);
#endif
#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
/* Configure ADC34 clock */
regval = getreg32(STM32_RCC_CFGR2);
regval &= ~RCC_CFGR2_ADC34PRES_MASK;
regval |= RCC_CFGR2_ADC34PRESd1;
putreg32(regval, STM32_RCC_CFGR2);
#endif
}
#endif

17
arch/arm/src/stm32/stm32f33xxx_rcc.c
View File

@ -52,6 +52,14 @@
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/* Max ADC clock frequency is 72MHz */
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
# if STM32_PLL_FREQUENCY > 72000000
# error ADCxxPRES is hardcoded to 1 - PLL frequency is too high
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -486,6 +494,15 @@ static void stm32_stdclockconfig(void)
regval |= RCC_CFGR3_HRTIM1SW;
putreg32(regval, STM32_RCC_CFGR3);
#endif
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
/* Configure ADC12 clock */
regval = getreg32(STM32_RCC_CFGR2);
regval &= ~RCC_CFGR2_ADC12PRES_MASK;
regval |= RCC_CFGR2_ADC12PRESd1;
putreg32(regval, STM32_RCC_CFGR2);
#endif
}
#endif