diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig
index 357807cdbe..2a5dbdcf67 100644
--- a/arch/xtensa/src/esp32s2/Kconfig
+++ b/arch/xtensa/src/esp32s2/Kconfig
@@ -192,6 +192,10 @@ config ESP32S2_RUN_IRAM
 
 menu "ESP32-S2 Peripheral Selection"
 
+config ESP32S2_UART
+	bool
+	default n
+
 config ESP32S2_UART
 	bool
 	default n
@@ -380,12 +384,6 @@ config ESP32S2_UART1
 	select UART1_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
-config ESP32S2_UART2
-	bool "UART 2"
-	default n
-	select ESP32S2_UART
-	select UART2_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
 
 config ESP32S2_WIRELESS
 	bool "Wireless"
@@ -450,72 +448,22 @@ config ESP32S2_UART0_RXPIN
 	default 44
 	range 0 46
 
-if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
-config ESP32S2_UART0_RTSPIN
-	int "UART0 RTS Pin"
-	default 22
-	range 0 39
-
-config ESP32S2_UART0_CTSPIN
-	int "UART0 CTS Pin"
-	default 19
-	range 0 39
-
-endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
 endif # ESP32S2_UART0
 
 if ESP32S2_UART1
 
 config ESP32S2_UART1_TXPIN
 	int "UART1 Tx Pin"
-	default 10
-	range 0 39
+	default 17
+	range 0 46
 
 config ESP32S2_UART1_RXPIN
 	int "UART1 Rx Pin"
-	default 9
-	range 0 39
+	default 18
+	range 0 46
 
-if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
-config ESP32S2_UART1_RTSPIN
-	int "UART1 RTS Pin"
-	default 11
-	range 0 39
-
-config ESP32S2_UART1_CTSPIN
-	int "UART1 CTS Pin"
-	default 6
-	range 0 39
-
-endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
 endif # ESP32S2_UART1
 
-if ESP32S2_UART2
-
-config ESP32S2_UART2_TXPIN
-	int "UART2 Tx Pin"
-	default 17
-	range 0 39
-
-config ESP32S2_UART2_RXPIN
-	int "UART2 Rx Pin"
-	default 16
-	range 0 39
-
-if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
-config ESP32S2_UART2_RTSPIN
-	int "UART2 RTS Pin"
-	default 7
-	range 0 39
-
-config ESP32S2_UART2_CTSPIN
-	int "UART2 CTS Pin"
-	default 8
-	range 0 39
-
-endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
-endif # ESP32S2_UART2
-
 endmenu # UART configuration
 
 menu "I2C configuration"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c
index 105eb808b4..e6ac5170e5 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c
@@ -63,11 +63,11 @@ struct esp32s2_uart_s g_uart0_config =
   .periph = ESP32S2_PERI_UART,
   .id = 0,
   .cpuint = -ENOMEM,
-  .irq =  ESP32S2_IRQ_UART,
+  .irq = ESP32S2_IRQ_UART,
   .baud = CONFIG_UART0_BAUD,
   .bits = CONFIG_UART0_BITS,
   .parity = CONFIG_UART0_PARITY,
-  .stop_b2 =  CONFIG_UART0_2STOP,
+  .stop_b2 = CONFIG_UART0_2STOP,
   .int_pri = ESP32S2_INT_PRIO_DEF,
   .txpin = CONFIG_ESP32S2_UART0_TXPIN,
   .txsig = U0TXD_OUT_IDX,
@@ -88,7 +88,7 @@ struct esp32s2_uart_s g_uart1_config =
   .baud = CONFIG_UART1_BAUD,
   .bits = CONFIG_UART1_BITS,
   .parity = CONFIG_UART1_PARITY,
-  .stop_b2 =  CONFIG_UART1_2STOP,
+  .stop_b2 = CONFIG_UART1_2STOP,
   .int_pri = ESP32S2_INT_PRIO_DEF,
   .txpin = CONFIG_ESP32S2_UART1_TXPIN,
   .txsig = U1TXD_OUT_IDX,
@@ -221,7 +221,7 @@ uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s * priv)
   uint32_t clk_conf_reg;
   uint32_t ret = -ENODATA;
   uint32_t clk;
-  clk_conf_reg   = getreg32(UART_CONF0_REG(priv->id));
+  clk_conf_reg = getreg32(UART_CONF0_REG(priv->id));
   clk = REG_MASK(clk_conf_reg, UART_TICK_REF_ALWAYS_ON);
   if (clk == 1)
     {
@@ -232,6 +232,9 @@ uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s * priv)
       /* TODO in esp32s2_clockconfig.c
        * ret = esp32s2_clk_ref_freq();
        */
+
+      _warn("esp32s2_clockconfig.c still doesn't support "
+            "esp32s2_clk_ref_freq() ");
     }
 
   return ret;
@@ -583,11 +586,15 @@ void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv)
 
   esp32s2_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
 
-  /* Select the GPIO function to the TX pin and configure as output. */
+  /* Select the GPIO function to the TX pin and
+   * configure as output.
+   */
 
   esp32s2_configgpio(priv->txpin, OUTPUT_FUNCTION_1);
 
-  /* Select the GPIO function to the RX pin and configure as input. */
+  /* Select the GPIO function to the RX pin and
+   * configure as input.
+   */
 
   esp32s2_configgpio(priv->rxpin, INPUT_FUNCTION_1);
 
@@ -611,11 +618,11 @@ void up_lowputc(char ch)
 {
 #ifdef HAVE_SERIAL_CONSOLE
 
-#  if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
   struct esp32s2_uart_s *priv = &g_uart0_config;
 #elif defined (CONFIG_UART1_SERIAL_CONSOLE)
   struct esp32s2_uart_s *priv = &g_uart1_config;
-#endif
+# endif
 
   /* Wait until the TX FIFO has space to insert new char */
 
diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c
index c401f7bfbb..5110b1dfb6 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_serial.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c
@@ -53,10 +53,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* The console is enabled, and it's not the syslog device,
- * so, it should be a serial device.
- */
-
 #ifdef USE_SERIALDRIVER
 
 /* Which UART will be tty0/console and which tty1? */
@@ -658,7 +654,7 @@ static int esp32s2_receive(struct uart_dev_s *dev, unsigned int *status)
   struct esp32s2_uart_s *priv = dev->priv;
 
   rx_fifo = getreg32(UART_FIFO_REG(priv->id));
-  rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+  rx_fifo = REG_MASK(rx_fifo, UART_RXFIFO_RD_BYTE);
 
   /* Since we don't have error bits associated with receipt, we set zero */