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imxrt: Style fixes in mux and ADC hardware headers

This commit is contained in:
Thomas Axelsson 2020-09-23 16:13:02 +02:00 committed by Alan Carvalho de Assis
parent d67bc0c3c8
commit f193f0f702
2 changed files with 64 additions and 58 deletions
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87
arch/arm/src/imxrt/hardware/imxrt_adc.h
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@ -74,11 +74,11 @@
#define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */
#define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */
/* Register addresses ***********************************************************************/
/* Register addresses ***************************************************************/
/* ADC1 Register Addresses */
#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC1 (IMXRT_ADC1_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC2 (IMXRT_ADC1_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC3 (IMXRT_ADC1_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC1 Control register for hardware triggers */
@ -104,7 +104,7 @@
/* ADC2 Register Addresses */
#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC1 (IMXRT_ADC2_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC2 (IMXRT_ADC2_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC3 (IMXRT_ADC2_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC2 Control register for hardware triggers */
@ -135,16 +135,16 @@
#define ADC_HC_ADCH_SHIFT (0) /* Bits: 0-4 Input Channel Select */
#define ADC_HC_ADCH_MASK (31 << ADC_HC_ADCH_SHIFT)
# define ADC_HC_ADCH(n) ((uint32_t)(n) << ADC_HC_ADCH_SHIFT)
# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */
# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */
# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */
# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */
# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */
# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */
# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */
# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */
# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */
# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */
# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */
# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */
# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */
# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */
# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */
# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */
# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */
# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */
# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */
# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */
# define ADC_HC_ADCH_EXT_10 (10 << ADC_HC_ADCH_SHIFT) /* External channels 10 */
# define ADC_HC_ADCH_EXT_11 (11 << ADC_HC_ADCH_SHIFT) /* External channels 11 */
# define ADC_HC_ADCH_EXT_12 (12 << ADC_HC_ADCH_SHIFT) /* External channels 12 */
@ -154,7 +154,8 @@
# define ADC_HC_ADCH_EXT_ADC_ETC (16 << ADC_HC_ADCH_SHIFT) /* External channel selection from ADC_ETC */
# define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */
# define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */
/* Bits: 5-6 Reserved */
/* Bits: 5-6 Reserved */
#define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */
/* Bits: 8-31 Reserved */
@ -170,51 +171,51 @@
/* Configuration register */
#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */
#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */
#define ADC_CFG_ADICLK_MASK (3 << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK(n) ((uint32_t)(n) << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK_IPG (0 << ADC_CFG_ADICLK_SHIFT) /* IPG clock */
# define ADC_CFG_ADICLK_IPGDIV2 (1 << ADC_CFG_ADICLK_SHIFT) /* IPG clock divided by 2 */
# define ADC_CFG_ADICLK_ADACK (3 << ADC_CFG_ADICLK_SHIFT) /* Asynchronous clock (ADACK) */
#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */
#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */
#define ADC_CFG_MODE_MASK (3 << ADC_CFG_MODE_SHIFT)
# define ADC_CFG_MODE(n) ((uint32_t)(n) << ADC_CFG_MODE_SHIFT)
# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */
# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */
# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */
#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */
#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */
# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */
# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */
# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */
#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */
#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */
#define ADC_CFG_ADIV_MASK (3 << ADC_CFG_ADIV_SHIFT)
# define ADC_CFG_ADIV(n) ((uint32_t)(n) << ADC_CFG_ADIV_SHIFT)
# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */
# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */
# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */
# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */
#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */
#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */
# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */
# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */
# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */
#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */
#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
#define ADC_CFG_ADSTS_MASK (3 << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS(n) ((uint32_t)(n) << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS_3_13 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 3 if ADLSMP=0b, 13 if ADLSMP=1b */
# define ADC_CFG_ADSTS_5_17 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 5 if ADLSMP=0b, 17 if ADLSMP=1b */
# define ADC_CFG_ADSTS_7_21 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 7 if ADLSMP=0b, 21 if ADLSMP=1b */
# define ADC_CFG_ADSTS_9_25 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 9 if ADLSMP=0b, 25 if ADLSMP=1b */
#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
# define ADC_CFG_ADSTS_3_13 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 3 if ADLSMP=0b, 13 if ADLSMP=1b */
# define ADC_CFG_ADSTS_5_17 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 5 if ADLSMP=0b, 17 if ADLSMP=1b */
# define ADC_CFG_ADSTS_7_21 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 7 if ADLSMP=0b, 21 if ADLSMP=1b */
# define ADC_CFG_ADSTS_9_25 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 9 if ADLSMP=0b, 25 if ADLSMP=1b */
#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
#define ADC_CFG_REFSEL_MASK (3 << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL(n) ((uint32_t)(n) << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL_VREF (0 << ADC_CFG_REFSEL_SHIFT) /* Selects VREFH/VREFL as reference voltage. */
#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */
# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */
# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */
#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */
#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */
# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */
# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */
#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */
#define ADC_CFG_AVGS_MASK (3 << ADC_CFG_AVGS_SHIFT)
# define ADC_CFG_AVGS(n) ((uint32_t)(n) << ADC_CFG_AVGS_SHIFT)
# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */
# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */
# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */
# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */
#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */
/* Bits: 17-31 Reserved */
# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */
# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */
# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */
# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */
#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */
/* Bits: 17-31 Reserved */
/* General control register */

35
arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
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@ -93,32 +93,37 @@
#define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */
#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */
#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT)
# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */
# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */
#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT)
# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */
# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */
#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */
#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */
#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */
#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT)
# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */
# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */
/* Defaults for drive conditions for each set of pins. These are a good