drivers: restore C89 compatibility by avoiding binary constants

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko 2023-07-31 20:45:14 +02:00 committed by Xiang Xiao
parent f3b5465969
commit effb0a1cad
4 changed files with 16 additions and 16 deletions

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@ -1209,7 +1209,7 @@ static void mcp2515_reset_lowlevel(FAR struct mcp2515_can_s *priv)
/* Make sure that all buffers are released. */
nxsem_reset(&priv->txfsem, MCP2515_NUM_TX_BUFFERS);
priv->txbuffers = 0b111;
priv->txbuffers = (1 << MCP2515_NUM_TX_BUFFERS) - 1;
/* Define the current state and unlock */
@ -2540,7 +2540,7 @@ FAR struct mcp2515_can_s *
/* Initialize bitmask */
priv->txbuffers = (1 << MCP2515_NUM_TX_BUFFERS)-1;
priv->txbuffers = (1 << MCP2515_NUM_TX_BUFFERS) - 1;
/* And put the hardware in the initial state */

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@ -294,7 +294,7 @@ static int i2c_bitbang_wait_ack(FAR struct i2c_bitbang_dev_s *priv)
static void i2c_bitbang_send(FAR struct i2c_bitbang_dev_s *priv,
uint8_t data)
{
uint8_t bit = 0b10000000;
uint8_t bit = 1u << 7;
while (bit)
{

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@ -38,24 +38,24 @@
enum hall3_120deg_position_e
{
HALL3_120DEG_POS_1 = 0b001,
HALL3_120DEG_POS_2 = 0b011,
HALL3_120DEG_POS_3 = 0b010,
HALL3_120DEG_POS_4 = 0b110,
HALL3_120DEG_POS_5 = 0b100,
HALL3_120DEG_POS_6 = 0b101
HALL3_120DEG_POS_1 = 1, /* 0b001 */
HALL3_120DEG_POS_2 = 3, /* 0b011 */
HALL3_120DEG_POS_3 = 2, /* 0b010 */
HALL3_120DEG_POS_4 = 6, /* 0b110 */
HALL3_120DEG_POS_5 = 4, /* 0b100 */
HALL3_120DEG_POS_6 = 5 /* 0b101 */
};
/* 60-degree Hall effect sensors positions */
enum hall3_60deg_position_e
{
HALL3_60DEG_POS_1 = 0b000,
HALL3_60DEG_POS_2 = 0b001,
HALL3_60DEG_POS_3 = 0b101,
HALL3_60DEG_POS_4 = 0b111,
HALL3_60DEG_POS_5 = 0b110,
HALL3_60DEG_POS_6 = 0b010
HALL3_60DEG_POS_1 = 0, /* 0b000 */
HALL3_60DEG_POS_2 = 1, /* 0b001 */
HALL3_60DEG_POS_3 = 5, /* 0b101 */
HALL3_60DEG_POS_4 = 7, /* 0b111 */
HALL3_60DEG_POS_5 = 6, /* 0b110 */
HALL3_60DEG_POS_6 = 2 /* 0b010 */
};
/* This structure provides the "lower-half" driver operations available to

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@ -84,7 +84,7 @@ enum accel_config_bit
ACCEL_FS_SEL_2G = 0, /* 0b00000 */
ACCEL_FS_SEL_4G = 1, /* 0b01000 */
ACCEL_FS_SEL_8G = 2, /* 0b10000 */
ACCEL_FS_SEL_16G = 3, /* 0b11000 */
ACCEL_FS_SEL_16G = 3 /* 0b11000 */
};
/* These structures are defined elsewhere, and we don't need their