Completes bit definitions for STM32 USB OTG FS registers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4481 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
57b9d9c1de
commit
e64511c105
|
|
@ -414,12 +414,12 @@
|
|||
/* USB configuration register */
|
||||
|
||||
#define OTGFS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
|
||||
#define OTGFS_GUSBCFG_TOCAL_MASK (7 < OTGFS_GUSBCFG_TOCAL_SHIFT)
|
||||
#define OTGFS_GUSBCFG_TOCAL_MASK (7 << OTGFS_GUSBCFG_TOCAL_SHIFT)
|
||||
/* Bits 3-6: Reserved, must be kept at reset value */
|
||||
#define OTGFS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */
|
||||
#define OTGFS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */
|
||||
#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
|
||||
#define OTGFS_GUSBCFG_TRDT_MASK (15 < OTGFS_GUSBCFG_TRDT_SHIFT)
|
||||
#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT)
|
||||
/* Bits 14-28: Reserved, must be kept at reset value */
|
||||
#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
|
||||
#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
|
||||
|
|
@ -434,12 +434,12 @@
|
|||
#define OTGFS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
|
||||
#define OTGFS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
|
||||
#define OTGFS_GRSTCTL_TXFNUM_SHIFT (10) /* Bits 6-10: TxFIFO number */
|
||||
#define OTGFS_GRSTCTL_TXFNUM_MASK (31 < OTGFS_GRSTCTL_TXFNUM_SHIFT)
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 < OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HPER (1 < OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HALL (16 < OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/
|
||||
# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) < OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_DALL (16 < OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/
|
||||
#define OTGFS_GRSTCTL_TXFNUM_MASK (31 << OTGFS_GRSTCTL_TXFNUM_SHIFT)
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HPER (1 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_HALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/
|
||||
# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */
|
||||
# define OTGFS_GRSTCTL_TXFNUM_DALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/
|
||||
/* Bits 11-31: Reserved, must be kept at reset value */
|
||||
#define OTGFS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */
|
||||
|
||||
|
|
@ -479,43 +479,43 @@
|
|||
/* Receive status debug read/OTG status read and pop registers (host mode) */
|
||||
|
||||
#define OTGFS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */
|
||||
#define OTGFS_GRXSTSH_CHNUM_MASK (15 < OTGFS_GRXSTSH_CHNUM_SHIFT)
|
||||
#define OTGFS_GRXSTSH_CHNUM_MASK (15 << OTGFS_GRXSTSH_CHNUM_SHIFT)
|
||||
#define OTGFS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
|
||||
#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff < OTGFS_GRXSTSH_BCNT_SHIFT)
|
||||
#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff << OTGFS_GRXSTSH_BCNT_SHIFT)
|
||||
#define OTGFS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */
|
||||
#define OTGFS_GRXSTSH_DPID_MASK (3 < OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA0 (0 < OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA2 (1 < OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA1 (2 < OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_MDATA (3 < OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
#define OTGFS_GRXSTSH_DPID_MASK (3 << OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA0 (0 << OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA2 (1 << OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_DATA1 (2 << OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSH_DPID_MDATA (3 << OTGFS_GRXSTSH_DPID_SHIFT)
|
||||
#define OTGFS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
|
||||
#define OTGFS_GRXSTSH_PKTSTS_MASK (15 < OTGFS_GRXSTSH_PKTSTS_SHIFT)
|
||||
# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 < OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 < OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (2 < OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 < OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
|
||||
#define OTGFS_GRXSTSH_PKTSTS_MASK (15 << OTGFS_GRXSTSH_PKTSTS_SHIFT)
|
||||
# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
|
||||
# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
|
||||
/* Bits 21-31: Reserved, must be kept at reset value.
|
||||
/* Receive status debug read/OTG status read and pop registers (device mode) */
|
||||
|
||||
#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
|
||||
#define OTGFS_GRXSTSD_EPNUM_MASK (15 < OTGFS_GRXSTSD_EPNUM_SHIFT)
|
||||
#define OTGFS_GRXSTSD_EPNUM_MASK (15 << OTGFS_GRXSTSD_EPNUM_SHIFT)
|
||||
#define OTGFS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
|
||||
#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff < OTGFS_GRXSTSD_BCNT_SHIFT)
|
||||
#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff << OTGFS_GRXSTSD_BCNT_SHIFT)
|
||||
#define OTGFS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */
|
||||
#define OTGFS_GRXSTSD_DPID_MASK (3 < OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA0 (0 < OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA2 (1 < OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA1 (2 < OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_MDATA (3 < OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
#define OTGFS_GRXSTSD_DPID_MASK (3 << OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA0 (0 << OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA2 (1 << OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_DATA1 (2 << OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
# define OTGFS_GRXSTSD_DPID_MDATA (3 << OTGFS_GRXSTSD_DPID_SHIFT)
|
||||
#define OTGFS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
|
||||
#define OTGFS_GRXSTSD_PKTSTS_MASK (15 < OTGFS_GRXSTSD_PKTSTS_SHIFT)
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 < OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 < OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 < OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 < OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 < OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
|
||||
#define OTGFS_GRXSTSD_PKTSTS_MASK (15 << OTGFS_GRXSTSD_PKTSTS_SHIFT)
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */
|
||||
# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
|
||||
#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
|
||||
#define OTGFS_GRXSTSD_FRMNUM_MASK (15 < OTGFS_GRXSTSD_FRMNUM_SHIFT)
|
||||
#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT)
|
||||
/* Bits 25-31: Reserved, must be kept at reset value.
|
||||
/* Receive FIFO size register */
|
||||
|
||||
|
|
@ -524,41 +524,41 @@
|
|||
/* Host non-periodic transmit FIFO size register */
|
||||
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff < OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT)
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT)
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff < OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 < OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 < OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
|
||||
|
||||
/* Endpoint 0 Transmit FIFO size */
|
||||
|
||||
#define OTGFS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */
|
||||
#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff < OTGFS_DIEPTXF0_TX0FD_SHIFT)
|
||||
#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff << OTGFS_DIEPTXF0_TX0FD_SHIFT)
|
||||
#define OTGFS_DIEPTXF0_NPTXFD_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */
|
||||
#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff < OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 < OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 < OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
|
||||
|
||||
/* Non-periodic transmit FIFO/queue status register */
|
||||
|
||||
#define OTGFS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */
|
||||
#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff < OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 < OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */
|
||||
#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff < OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 < OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
|
||||
#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f < OTGFS_HNPTXSTS_NPTXQTOP_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGFS_HNPTXSTS_NPTXQTOP_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
|
||||
# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
|
||||
# define OTGFS_HNPTXSTS_TYPE_MASK (3 < OTGFS_HNPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_TYPE_INOUT (0 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HNPTXSTS_TYPE_ZLP (1 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
|
||||
# define OTGFS_HNPTXSTS_TYPE_HALT (3 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
|
||||
# define OTGFS_HNPTXSTS_TYPE_MASK (3 << OTGFS_HNPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_TYPE_INOUT (0 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HNPTXSTS_TYPE_ZLP (1 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
|
||||
# define OTGFS_HNPTXSTS_TYPE_HALT (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
|
||||
# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
|
||||
# define OTGFS_HNPTXSTS_CHNUM_MASK (15 < OTGFS_HNPTXSTS_CHNUM_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_CHNUM_MASK (15 << OTGFS_HNPTXSTS_CHNUM_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
|
||||
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 < OTGFS_HNPTXSTS_EPNUM_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
|
||||
/* Bit 31 Reserved, must be kept at reset value */
|
||||
/* general core configuration register */
|
||||
/* Bits 15:0 Reserved, must be kept at reset value */
|
||||
|
|
@ -574,26 +574,26 @@
|
|||
/* Host periodic transmit FIFO size register */
|
||||
|
||||
#define OTGFS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */
|
||||
#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff < OTGFS_HPTXFSIZ_PTXSA_SHIFT)
|
||||
#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGFS_HPTXFSIZ_PTXSA_SHIFT)
|
||||
#define OTGFS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */
|
||||
#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff < OTGFS_HPTXFSIZ_PTXFD_SHIFT)
|
||||
#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGFS_HPTXFSIZ_PTXFD_SHIFT)
|
||||
|
||||
/* Device IN endpoint transmit FIFOn size register */
|
||||
|
||||
#define OTGFS_DIEPTXF1_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */
|
||||
#define OTGFS_DIEPTXF1_INEPTXSA_MASK (0xffff < OTGFS_DIEPTXF1_INEPTXSA_SHIFT)
|
||||
#define OTGFS_DIEPTXF1_INEPTXSA_MASK (0xffff << OTGFS_DIEPTXF1_INEPTXSA_SHIFT)
|
||||
#define OTGFS_DIEPTXF1_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */
|
||||
#define OTGFS_DIEPTXF1_INEPTXFD_MASK (0xffff < OTGFS_DIEPTXF1_INEPTXFD_SHIFT)
|
||||
#define OTGFS_DIEPTXF1_INEPTXFD_MASK (0xffff << OTGFS_DIEPTXF1_INEPTXFD_SHIFT)
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
/* Host configuration register */
|
||||
|
||||
#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
|
||||
#define OTGFS_HCFG_FSLSPCS_MASK (3 < OTGFS_HCFG_FSLSPCS_SHIFT)
|
||||
# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 < OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 < OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 < OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
|
||||
#define OTGFS_HCFG_FSLSPCS_MASK (3 << OTGFS_HCFG_FSLSPCS_SHIFT)
|
||||
# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
|
||||
#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
|
||||
/* Bits 31:3 Reserved, must be kept at reset value */
|
||||
/* Host frame interval register */
|
||||
|
|
@ -603,28 +603,28 @@
|
|||
/* Host frame number/frame time remaining register */
|
||||
|
||||
#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */
|
||||
#define OTGFS_HFNUM_FRNUM_MASK (0xffff < OTGFS_HFNUM_FRNUM_SHIFT)
|
||||
#define OTGFS_HFNUM_FRNUM_MASK (0xffff << OTGFS_HFNUM_FRNUM_SHIFT)
|
||||
#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */
|
||||
#define OTGFS_HFNUM_FTREM_MASK (0xffff < OTGFS_HFNUM_FTREM_SHIFT)
|
||||
#define OTGFS_HFNUM_FTREM_MASK (0xffff << OTGFS_HFNUM_FTREM_SHIFT)
|
||||
|
||||
/* Host periodic transmit FIFO/queue status register */
|
||||
|
||||
#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
|
||||
#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff < OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 < OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 << OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
|
||||
#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff < OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 < OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff << OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 << OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
|
||||
#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f < OTGFS_HPTXSTS_PTXQTOP_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGFS_HPTXSTS_PTXQTOP_SHIFT)
|
||||
# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
|
||||
# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
|
||||
# define OTGFS_HPTXSTS_TYPE_MASK (3 < OTGFS_HPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HPTXSTS_TYPE_INOUT (0 < OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HPTXSTS_TYPE_ZLP (1 < OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
|
||||
# define OTGFS_HPTXSTS_TYPE_HALT (3 < OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
|
||||
# define OTGFS_HPTXSTS_TYPE_MASK (3 << OTGFS_HPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HPTXSTS_TYPE_INOUT (0 << OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HPTXSTS_TYPE_ZLP (1 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
|
||||
# define OTGFS_HPTXSTS_TYPE_HALT (3 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
|
||||
# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
|
||||
# define OTGFS_HPTXSTS_EPNUM_MASK (15 < OTGFS_HPTXSTS_EPNUM_SHIFT)
|
||||
# define OTGFS_HPTXSTS_EPNUM_MASK (15 << OTGFS_HPTXSTS_EPNUM_SHIFT)
|
||||
# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */
|
||||
|
||||
/* Host all channels interrupt and all channels interrupt mask registers */
|
||||
|
|
@ -633,140 +633,353 @@
|
|||
|
||||
/* Host port control and status register */
|
||||
|
||||
#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
|
||||
#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
|
||||
#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
|
||||
#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
|
||||
#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
|
||||
#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
|
||||
#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
|
||||
#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
|
||||
#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
|
||||
/* Bit 9 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
|
||||
#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
|
||||
#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
|
||||
#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
|
||||
#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
|
||||
#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
|
||||
#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
|
||||
#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
|
||||
#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
|
||||
/* Bit 9: Reserved, must be kept at reset value */
|
||||
#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
|
||||
#define OTGFS_HPRT_PLSTS_MASK (3 < OTGFS_HPRT_PLSTS_SHIFT)
|
||||
#define OTGFS_HPRT_PLSTS_MASK (3 << OTGFS_HPRT_PLSTS_SHIFT)
|
||||
# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
|
||||
# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
|
||||
#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
|
||||
#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
|
||||
#define OTGFS_HPRT_PTCTL_MASK (15 < OTGFS_HPRT_PTCTL_SHIFT)
|
||||
# define OTGFS_HPRT_PTCTL_DISABLED (0 < OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */
|
||||
# define OTGFS_HPRT_PTCTL_J (1 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */
|
||||
# define OTGFS_HPRT_PTCTL_L (2 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */
|
||||
# define OTGFS_HPRT_PTCTL_SE0_NAK (3 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
|
||||
# define OTGFS_HPRT_PTCTL_PACKET (4 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
|
||||
# define OTGFS_HPRT_PTCTL_FORCE (5 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
|
||||
#define OTGFS_HPRT_PTCTL_MASK (15 << OTGFS_HPRT_PTCTL_SHIFT)
|
||||
# define OTGFS_HPRT_PTCTL_DISABLED (0 << OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */
|
||||
# define OTGFS_HPRT_PTCTL_J (1 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */
|
||||
# define OTGFS_HPRT_PTCTL_L (2 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */
|
||||
# define OTGFS_HPRT_PTCTL_SE0_NAK (3 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
|
||||
# define OTGFS_HPRT_PTCTL_PACKET (4 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
|
||||
# define OTGFS_HPRT_PTCTL_FORCE (5 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
|
||||
#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
|
||||
#define OTGFS_HPRT_PSPD_MASK (3 < OTGFS_HPRT_PSPD_SHIFT)
|
||||
# define OTGFS_HPRT_PSPD_FS (1 < OTGFS_HPRT_PSPD_SHIFT) /* Full speed */
|
||||
# define OTGFS_HPRT_PSPD_LS (2 < OTGFS_HPRT_PSPD_SHIFT) /* Low speed */
|
||||
/* Bits 31:19 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HPRT_PSPD_MASK (3 << OTGFS_HPRT_PSPD_SHIFT)
|
||||
# define OTGFS_HPRT_PSPD_FS (1 << OTGFS_HPRT_PSPD_SHIFT) /* Full speed */
|
||||
# define OTGFS_HPRT_PSPD_LS (2 << OTGFS_HPRT_PSPD_SHIFT) /* Low speed */
|
||||
/* Bits 19-31: Reserved, must be kept at reset value */
|
||||
|
||||
/* Host channel-n characteristics register */
|
||||
|
||||
#define OTGFS_HCCHAR0_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
|
||||
#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff < OTGFS_HCCHAR_MPSIZ_SHIFT)
|
||||
#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff << OTGFS_HCCHAR_MPSIZ_SHIFT)
|
||||
#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
|
||||
#define OTGFS_HCCHAR_EPNUM_MASK (15 < OTGFS_HCCHAR_EPNUM_SHIFT)
|
||||
#define OTGFS_HCCHAR_EPNUM_MASK (15 << OTGFS_HCCHAR_EPNUM_SHIFT)
|
||||
#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
|
||||
# define OTGFS_HCCHAR_EPDIR_OUT (0)
|
||||
# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR
|
||||
/* Bit 16 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
|
||||
#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_HCCHAR_EPTYP_MASK (3 < OTGFS_HCCHAR_EPTYP_SHIFT)
|
||||
# define OTGFS_HCCHAR_EPTYP_CTRL (0 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */
|
||||
# define OTGFS_HCCHAR_EPTYP_ISOC (1 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */
|
||||
# define OTGFS_HCCHAR_EPTYP_BULK (2 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */
|
||||
# define OTGFS_HCCHAR_EPTYP_INTR (3 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */
|
||||
#define OTGFS_HCCHAR_EPTYP_MASK (3 << OTGFS_HCCHAR_EPTYP_SHIFT)
|
||||
# define OTGFS_HCCHAR_EPTYP_CTRL (0 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */
|
||||
# define OTGFS_HCCHAR_EPTYP_ISOC (1 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */
|
||||
# define OTGFS_HCCHAR_EPTYP_BULK (2 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */
|
||||
# define OTGFS_HCCHAR_EPTYP_INTR (3 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */
|
||||
#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
|
||||
#define OTGFS_HCCHAR_MCNT_MASK (3 < OTGFS_HCCHAR_MCNT_SHIFT)
|
||||
#define OTGFS_HCCHAR_MCNT_MASK (3 << OTGFS_HCCHAR_MCNT_SHIFT)
|
||||
#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
|
||||
#define OTGFS_HCCHAR_DAD_MASK (0x7f < OTGFS_HCCHAR_DAD_SHIFT)
|
||||
#define OTGFS_HCCHAR_DAD_MASK (0x7f << OTGFS_HCCHAR_DAD_SHIFT)
|
||||
#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
|
||||
#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
|
||||
#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
|
||||
|
||||
/* Host channel-n interrupt and Host channel-0 interrupt mask registers */
|
||||
|
||||
#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
|
||||
#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
|
||||
/* Bit 2 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
|
||||
#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
|
||||
#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
|
||||
#define OTGFS_HCINTMSK_NYET (1 << 6) /* Bit 6: response received interrupt mask */
|
||||
#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
|
||||
#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
|
||||
#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
|
||||
#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
|
||||
#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
|
||||
/* Bit 2: Reserved, must be kept at reset value */
|
||||
#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
|
||||
#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
|
||||
#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
|
||||
#define OTGFS_HCINTMSK_NYET (1 << 6) /* Bit 6: response received interrupt mask */
|
||||
#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
|
||||
#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
|
||||
#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
|
||||
#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */
|
||||
/* Bits 31:11 Reserved, must be kept at reset value */
|
||||
/* Bits 11-31 Reserved, must be kept at reset value */
|
||||
/* Host channel-n interrupt register */
|
||||
|
||||
#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
|
||||
#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff < OTGFS_HCTSIZ_XFRSIZ_SHIFT)
|
||||
#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_HCTSIZ_XFRSIZ_SHIFT)
|
||||
#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */
|
||||
#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff < OTGFS_HCTSIZ_PKTCNT_SHIFT)
|
||||
#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGFS_HCTSIZ_PKTCNT_SHIFT)
|
||||
#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */
|
||||
#define OTGFS_HCTSIZ_DPID_MASK (3 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA0 (0 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA2 (1 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA1 (2 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_MDATA (3 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
#define OTGFS_HCTSIZ_DPID_MASK (3 << OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA0 (0 << OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA2 (1 << OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
/* Bit 31 Reserved, must be kept at reset value */
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
/* Device configuration register */
|
||||
#define OTGFS_DCFG_
|
||||
/* Device control register */
|
||||
#define OTGFS_DCTL_
|
||||
/* Device status register */
|
||||
#define OTGFS_DSTS_
|
||||
/* Device IN endpoint common interrupt mask register */
|
||||
#define OTGFS_DIEPMSK_
|
||||
/* Device OUT endpoint common interrupt mask register */
|
||||
#define OTGFS_DOEPMSK_
|
||||
/* Device all endpoints interrupt register */
|
||||
#define OTGFS_DAINT_
|
||||
/* All endpoints interrupt mask register */
|
||||
#define OTGFS_DAINTMSK_
|
||||
/* Device VBUS discharge time register */
|
||||
#define OTGFS_DVBUSDIS_
|
||||
/* Device VBUS pulsing time register */
|
||||
#define OTGFS_DVBUSPULSE_
|
||||
/* Device IN endpoint FIFO empty interrupt mask register */
|
||||
#define OTGFS_DIEPEMPMSK_
|
||||
/* Device control IN endpoint 0 control register */
|
||||
#define OTGFS_DIEPCTL0_
|
||||
/* Device control IN endpoint n control register */
|
||||
#define OTGFS_DIEPCTL1_
|
||||
/* Device endpoint-n interrupt register */
|
||||
#define OTGFS_DIEPINT_
|
||||
/* Device IN endpoint 0 transfer size register */
|
||||
#define OTGFS_DIEPTSIZ0_
|
||||
/* Device IN endpoint n transfer size register */
|
||||
#define OTGFS_DIEPTSIZ_
|
||||
/* Device OUT endpoint-0 transfer size register */
|
||||
#define OTGFS_DTXFSTS_
|
||||
/* Device OUT endpoint 0 control register */
|
||||
#define OTGFS_DOEPCTL0_
|
||||
/* Device OUT endpoint n control register */
|
||||
#define OTGFS_DOEPCTL_
|
||||
/* Device endpoint-n interrupt register */
|
||||
#define OTGFS_DOEPINT_
|
||||
/* Device OUT endpoint-0 transfer size register */
|
||||
#define OTGFS_DOEPTSIZ0_
|
||||
/* Device OUT endpoint-n transfer size register */
|
||||
#define OTGFS_DOEPTSIZ_
|
||||
|
||||
#define OTGFS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
|
||||
#define OTGFS_DCFG_DSPD_MASK (3 << OTGFS_DCFG_DSPD_SHIFT)
|
||||
# define OTGFS_DCFG_DSPD_FS (3 << OTGFS_DCFG_DSPD_SHIFT) /* Full speed */
|
||||
#define OTGFS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
|
||||
/* Bit 3: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
|
||||
#define OTGFS_DCFG_DAD_MASK (0x7f << OTGFS_DCFG_DAD_SHIFT)
|
||||
#define OTGFS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
|
||||
#define OTGFS_DCFG_PFIVL_MASK (3 << OTGFS_DCFG_PFIVL_SHIFT)
|
||||
# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
|
||||
# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
|
||||
# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
|
||||
# define OTGFS_DCFG_PFIVL_85PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
|
||||
/* Bits 13-31 Reserved, must be kept at reset value */
|
||||
/* Device control register */
|
||||
|
||||
#define OTGFS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */
|
||||
#define OTGFS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */
|
||||
#define OTGFS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */
|
||||
#define OTGFS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */
|
||||
#define OTGFS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */
|
||||
#define OTGFS_DCTL_TCTL_MASK (7 << OTGFS_DCTL_TCTL_SHIFT)
|
||||
# define OTGFS_DCTL_TCTL_DISABLED (0 << OTGFS_DCTL_TCTL_SHIFT) /* Test mode disabled */
|
||||
# define OTGFS_DCTL_TCTL_J (1 << OTGFS_DCTL_TCTL_SHIFT) /* Test_J mode */
|
||||
# define OTGFS_DCTL_TCTL_K (2 << OTGFS_DCTL_TCTL_SHIFT) /* Test_K mode */
|
||||
# define OTGFS_DCTL_TCTL_SE0_NAK (3 << OTGFS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */
|
||||
# define OTGFS_DCTL_TCTL_PACKET (4 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Packet mode */
|
||||
# define OTGFS_DCTL_TCTL_FORCE (5 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */
|
||||
#define OTGFS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */
|
||||
#define OTGFS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */
|
||||
#define OTGFS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
|
||||
#define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
|
||||
#define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
|
||||
/* Bits 12-31: Reserved, must be kept at reset value */
|
||||
/* Device status register */
|
||||
|
||||
#define OTGFS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
|
||||
#define OTGFS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
|
||||
#define OTGFS_DSTS_ENUMSPD_MASK (3 << OTGFS_DSTS_ENUMSPD_SHIFT)
|
||||
# define OTGFS_DSTS_ENUMSPD_FS (3 << OTGFS_DSTS_ENUMSPD_MASK) /* Full speed */
|
||||
/* Bits 4-7: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
|
||||
#define OTGFS_DSTS_FNSOF_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
|
||||
#define OTGFS_DSTS_FNSOF_MASK (0x3fff << OTGFS_DSTS_FNSOF_MASK)
|
||||
/* Bits 22-31: Reserved, must be kept at reset value */
|
||||
/* Device IN endpoint common interrupt mask register */
|
||||
|
||||
#define OTGFS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
|
||||
#define OTGFS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
|
||||
/* Bit 2: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
|
||||
#define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */
|
||||
#define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */
|
||||
#define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */
|
||||
/* Bits 7-31: Reserved, must be kept at reset value */
|
||||
/* Device OUT endpoint common interrupt mask register */
|
||||
|
||||
#define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
|
||||
#define OTGFS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
|
||||
/* Bit 2: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */
|
||||
#define OTGFS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */
|
||||
/* Bits 5-31: Reserved, must be kept at reset value */
|
||||
/* Device all endpoints interrupt and All endpoints interrupt mask registers */
|
||||
|
||||
#define OTGFS_DAINT_IEP(n) (1 << (n)) /* Bits 0-15: IN endpoint interrupt bits */
|
||||
#define OTGFS_DAINT_OEP(n) (1 << ((n)+16)) /* Bits 16-31: OUT endpoint interrupt bits */
|
||||
|
||||
/* Device VBUS discharge time register */
|
||||
|
||||
#define OTGFS_DVBUSDIS_MASK (0xffff)
|
||||
|
||||
/* Device VBUS pulsing time register */
|
||||
|
||||
#define OTGFS_DVBUSPULSE_MASK (0xfff)
|
||||
|
||||
/* Device IN endpoint FIFO empty interrupt mask register */
|
||||
|
||||
#define OTGFS_DIEPEMPMSK(n) (1 << (n))
|
||||
|
||||
/* Device control IN endpoint 0 control register */
|
||||
|
||||
#define OTGFS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
|
||||
#define OTGFS_DIEPCTL0_MPSIZ_MASK (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT)
|
||||
# define OTGFS_DIEPCTL0_MPSIZ_64 (0 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
|
||||
# define OTGFS_DIEPCTL0_MPSIZ_32 (1 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
|
||||
# define OTGFS_DIEPCTL0_MPSIZ_16 (2 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
|
||||
# define OTGFS_DIEPCTL0_MPSIZ_8 (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
|
||||
/* Bits 2-14: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
|
||||
/* Bit 16: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
|
||||
#define OTGFS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_DIEPCTL0_EPTYP_MASK (3 << OTGFS_DIEPCTL0_EPTYP_SHIFT)
|
||||
# define OTGFS_DIEPCTL0_EPTYP_CTRL (0 << OTGFS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
|
||||
/* Bit 20: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
|
||||
#define OTGFS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
|
||||
#define OTGFS_DIEPCTL0_TXFNUM_MASK (15 << OTGFS_DIEPCTL0_TXFNUM_SHIFT)
|
||||
#define OTGFS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
|
||||
#define OTGFS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
|
||||
/* Bits 28-29: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
|
||||
#define OTGFS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
|
||||
|
||||
/* Device control IN endpoint n control register */
|
||||
|
||||
#define OTGFS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
|
||||
#define OTGFS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DIEPCTL_MPSIZ_SHIFT)
|
||||
/* Bits 11-14: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
|
||||
#define OTGFS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
|
||||
# define OTGFS_DIEPCTL_EVEN (0)
|
||||
# define OTGFS_DIEPCTL_ODD OTGFS_DIEPCTL_EONUM
|
||||
# define OTGFS_DIEPCTL_DATA0 (0)
|
||||
# define OTGFS_DIEPCTL_DATA1 OTGFS_DIEPCTL_EONUM
|
||||
#define OTGFS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
|
||||
#define OTGFS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_DIEPCTL_EPTYP_MASK (3 << OTGFS_DIEPCTL_EPTYP_SHIFT)
|
||||
# define OTGFS_DIEPCTL_EPTYP_CTRL (0 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Control */
|
||||
# define OTGFS_DIEPCTL_EPTYP_ISOC (1 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
|
||||
# define OTGFS_DIEPCTL_EPTYP_BULK (2 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Bulk */
|
||||
# define OTGFS_DIEPCTL_EPTYP_INTR (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
|
||||
/* Bit 20: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
|
||||
#define OTGFS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
|
||||
#define OTGFS_DIEPCTL_TXFNUM_MASK (15 << OTGFS_DIEPCTL_TXFNUM_SHIFT)
|
||||
#define OTGFS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
|
||||
#define OTGFS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
|
||||
#define OTGFS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID */
|
||||
#define OTGFS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame */
|
||||
#define OTGFS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
|
||||
#define OTGFS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
|
||||
|
||||
/* Device endpoint-n interrupt register */
|
||||
|
||||
#define OTGFS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
|
||||
#define OTGFS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
|
||||
/* Bit 2: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */
|
||||
#define OTGFS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */
|
||||
/* Bit 5: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */
|
||||
#define OTGFS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */
|
||||
/* Bits 8-31: Reserved, must be kept at reset value */
|
||||
/* Device IN endpoint 0 transfer size register */
|
||||
|
||||
#define OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
|
||||
#define OTGFS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT)
|
||||
/* Bits 7-18: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
|
||||
#define OTGFS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGFS_DIEPTSIZ0_PKTCNT_SHIFT)
|
||||
/* Bits 21-31: Reserved, must be kept at reset value */
|
||||
/* Device IN endpoint n transfer size register */
|
||||
|
||||
#define OTGFS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
|
||||
#define OTGFS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT)
|
||||
#define OTGFS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
|
||||
#define OTGFS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DIEPTSIZ_PKTCNT_SHIFT)
|
||||
#define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
|
||||
#define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT)
|
||||
/* Bit 31: Reserved, must be kept at reset value */
|
||||
/* Device OUT endpoint-0 transfer size register */
|
||||
|
||||
#define OTGFS_DTXFSTS_MASK (0xffff)
|
||||
|
||||
/* Device OUT endpoint 0 control register */
|
||||
|
||||
#define OTGFS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
|
||||
#define OTGFS_DOEPCTL0_MPSIZ_MASK (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT)
|
||||
# define OTGFS_DOEPCTL0_MPSIZ_64 (0 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
|
||||
# define OTGFS_DOEPCTL0_MPSIZ_32 (1 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
|
||||
# define OTGFS_DOEPCTL0_MPSIZ_16 (2 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
|
||||
# define OTGFS_DOEPCTL0_MPSIZ_8 (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
|
||||
/* Bits 2-14: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
|
||||
/* Bit 16: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
|
||||
#define OTGFS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_DOEPCTL0_EPTYP_MASK (3 << OTGFS_DOEPCTL0_EPTYP_SHIFT)
|
||||
# define OTGFS_DOEPCTL0_EPTYP_CTRL (0 << OTGFS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
|
||||
#define OTGFS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
|
||||
#define OTGFS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
|
||||
/* Bits 22-25: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
|
||||
#define OTGFS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
|
||||
/* Bits 28-29: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
|
||||
#define OTGFS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
|
||||
|
||||
/* Device OUT endpoint n control register */
|
||||
|
||||
#define OTGFS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
|
||||
#define OTGFS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DOEPCTL_MPSIZ_SHIFT)
|
||||
/* Bits 11-14: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
|
||||
#define OTGFS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
|
||||
# define OTGFS_DOEPCTL_EVEN (0)
|
||||
# define OTGFS_DOEPCTL_ODD OTGFS_DOEPCTL_EONUM
|
||||
# define OTGFS_DOEPCTL_DATA0 (0)
|
||||
# define OTGFS_DOEPCTL_DATA1 OTGFS_DOEPCTL_EONUM
|
||||
#define OTGFS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
|
||||
#define OTGFS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_DOEPCTL_EPTYP_MASK (3 << OTGFS_DOEPCTL_EPTYP_SHIFT)
|
||||
# define OTGFS_DOEPCTL_EPTYP_CTRL (0 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Control */
|
||||
# define OTGFS_DOEPCTL_EPTYP_ISOC (1 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */
|
||||
# define OTGFS_DOEPCTL_EPTYP_BULK (2 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Bulk */
|
||||
# define OTGFS_DOEPCTL_EPTYP_INTR (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
|
||||
#define OTGFS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
|
||||
#define OTGFS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
|
||||
/* Bits 22-25: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
|
||||
#define OTGFS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
|
||||
#define OTGFS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID */
|
||||
#define OTGFS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID */
|
||||
#define OTGFS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
|
||||
#define OTGFS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
|
||||
|
||||
/* Device endpoint-n interrupt register */
|
||||
|
||||
#define OTGFS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
|
||||
#define OTGFS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
|
||||
/* Bit 2: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPINT_STUP (1 << 3) /* Bit 3: SETUP phase done */
|
||||
#define OTGFS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */
|
||||
/* Bit 5: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */
|
||||
/* Bits 7-31: Reserved, must be kept at reset value */
|
||||
/* Device OUT endpoint-0 transfer size register */
|
||||
|
||||
#define OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
|
||||
#define OTGFS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT)
|
||||
/* Bits 7-18: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */
|
||||
/* Bits 20-28: Reserved, must be kept at reset value */
|
||||
#define OTGFS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
|
||||
#define OTGFS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT)
|
||||
/* Bit 31: Reserved, must be kept at reset value */
|
||||
/* Device OUT endpoint-n transfer size register */
|
||||
|
||||
#define OTGFS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
|
||||
#define OTGFS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT)
|
||||
#define OTGFS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
|
||||
#define OTGFS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DOEPTSIZ_PKTCNT_SHIFT)
|
||||
#define OTGFS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
|
||||
#define OTGFS_DOEPTSIZ_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ_STUPCNT_SHIFT)
|
||||
#define OTGFS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */
|
||||
#define OTGFS_DOEPTSIZ_RXDPID_MASK (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
|
||||
# define OTGFS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
|
||||
# define OTGFS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
|
||||
# define OTGFS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
|
||||
# define OTGFS_DOEPTSIZ_RXDPID_MDATA (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
|
||||
/* Bit 31: Reserved, must be kept at reset value */
|
||||
/* Power and clock gating registers */
|
||||
|
||||
/* Power and clock gating control register */
|
||||
#define OTGFS_PCGCCTL_
|
||||
|
||||
(1 << xx) /* Bit nn:
|
||||
_SHIFT (nn) /* Bits nn-nn:
|
||||
_MASK (xx < yy)
|
||||
#define OTGFS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */
|
||||
#define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */
|
||||
/* Bits 2-3: Reserved, must be kept at reset value */
|
||||
#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
|
||||
/* Bits 5-31: Reserved, must be kept at reset value */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue