Fix STM32 F4 APB2 clock input frequencies
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4303 42af7a65-404d-4744-a932-0658087f49c3
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@ -2370,3 +2370,5 @@
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* arch/arm/src/stm32/stm32_pwm.c: Pulse count was limited to 128; now is
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(essentially) unlimited.
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* configs/stm3240g-eval/include/board.h: Input frequences wrong for all but
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one APB2 timer.
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@ -149,10 +149,10 @@
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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@ -142,10 +142,10 @@
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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