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ARM: Move L2 cache initialization to much later in the sequence

This commit is contained in:
Gregory Nutt 2014-07-27 10:03:33 -06:00
parent b57d2182ab
commit dd4be66f1c
8 changed files with 47 additions and 38 deletions
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4
arch/Kconfig
View File

@ -125,6 +125,10 @@ config ARCH_HAVE_IRQPRIO
bool
default n
config ARCH_L2CACHE
bool
default n
config CUSTOM_STACK
bool
default n

19
arch/arm/src/armv7-a/Kconfig
View File

@ -23,20 +23,11 @@ if ARMV7A_HAVE_L2CC
menu "L2 Cache Configuration"
config ARMV7A_L2CC
bool
default n
---help---
Set by the configuration tool if the architecture specific L2CC is
enabled. This is an architecture-independent setting to inform
firmware that an L2 cache is present and that standard L2 cache
operations are supported.
config ARMV7A_L2CC_PL310
bool "ARMv7-A L2CC P310 Support"
default n
depends on ARMV7A_HAVE_L2CC_PL310 && EXPERIMENTAL
select ARMV7A_L2CC
select ARCH_L2CACHE
---help---
Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
multi-way cache macrocell, version r3p2. The addition of an on-chip
@ -44,6 +35,7 @@ config ARMV7A_L2CC_PL310
method of improving the system performance when significant memory
traffic is generated by the processor.
if ARCH_L2CACHE
if ARMV7A_L2CC_PL310
config PL310_LOCKDOWN_BY_MASTER
@ -63,7 +55,7 @@ endif # ARMV7A_L2CC_PL310
choice
prompt "L2 Cache Associativity"
default ARMV7A_ASSOCIATIVITY_8WAY
depends on ARMV7A_L2CC
depends on ARCH_L2CACHE
---help---
This choice specifies the associativity of L2 cache in terms of the
number of ways. This value could be obtained by querying cache
@ -82,7 +74,7 @@ endchoice # L2 Cache Associativity
choice
prompt "L2 Cache Way Size"
default ARMV7A_WAYSIZE_16KB
depends on ARMV7A_L2CC
depends on ARCH_L2CACHE
---help---
This choice specifies size of each way. This value can be obtained
by querying cache configuration registers. However, by defining a
@ -108,8 +100,9 @@ config ARMV7A_WAYSIZE_512KB
bool "512 KiB"
endchoice # L2 Cache Associativity
endif # ARCH_L2CACHE
endmenu # L2 Cache Configuration
endif #
endif # ARMV7A_HAVE_L2CC
choice
prompt "Toolchain Selection"

23
arch/arm/src/armv7-a/arm_l2cc_pl310.c
View File

@ -172,10 +172,10 @@
/* Bit 25: Cache Replacement Policy
*
* Default: 0=Pseudo-random replacement using lfsr
* Default: 1=Round robin replacement policy
*/
#define L2CC_ACR_CRPOL_CONFIG (0) /* 0=Pseudo-random replacement */
#define L2CC_ACR_CRPOL_CONFIG L2CC_ACR_CRPOL /* 1=Round robin replacement policy */
/* Bit 26: Non-Secure Lockdown Enable
*
@ -293,7 +293,7 @@ static void pl310_flush_all(void)
****************************************************************************/
/***************************************************************************
* Name: l2cc_initialize
* Name: up_l2ccinitialize
*
* Description:
* One time configuration of the L2 cache. The L2 cache will be enabled
@ -304,11 +304,11 @@ static void pl310_flush_all(void)
* settings.
*
* Returned Value:
* Always returns OK.
* None
*
***************************************************************************/
int l2cc_initialize(void)
void up_l2ccinitialize(void)
{
uint32_t regval;
int i;
@ -326,10 +326,13 @@ int l2cc_initialize(void)
* cache configuration.
*/
#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
#else
# error No associativity selected
#endif
#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
@ -344,6 +347,8 @@ int l2cc_initialize(void)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
#else
# error No way size selected
#endif
/* L2 configuration can only be changed if the cache is disabled,
@ -389,8 +394,8 @@ int l2cc_initialize(void)
for (i = 0; i < PL310_NLOCKREGS; i++)
{
putreg32(0, L2CC_DLKR_OFFSET(i));
putreg32(0, L2CC_ILKR_OFFSET(i));
putreg32(0, L2CC_DLKR(i));
putreg32(0, L2CC_ILKR(i));
}
/* Configure the cache properties */
@ -408,8 +413,6 @@ int l2cc_initialize(void)
lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
return OK;
}
/***************************************************************************

2
arch/arm/src/armv7-a/cache.h
View File

@ -102,7 +102,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
static inline void arch_invalidate_dcache_all(void)
{
#ifdef CONFIG_ARMV7A_L2CC
#ifdef CONFIG_ARCH_L2CACHE
irqstate_t flags = irqsave();
cp15_invalidate_dcache_all();
l2cc_invalidate_all();

15
arch/arm/src/armv7-a/l2cc.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
#ifdef CONFIG_ARMV7A_L2CC
#ifdef CONFIG_ARCH_L2CACHE
/****************************************************************************
* Pre-processor Definitions
@ -67,7 +67,7 @@ extern "C"
****************************************************************************/
/***************************************************************************
* Name: l2cc_initialize
* Name: up_l2ccinitialize
*
* Description:
* One time configuration of the L2 cache. The L2 cache will be enabled
@ -78,11 +78,13 @@ extern "C"
* settings.
*
* Returned Value:
* Always returns OK.
* None
*
***************************************************************************/
int l2cc_initialize(void);
#if 0 /* Prototyped in up_internal.h */
void up_l2ccinitialize(void);
#endif
/***************************************************************************
* Name: l2cc_enable
@ -238,12 +240,11 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
#endif
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARMV7A_L2CC */
#else /* CONFIG_ARCH_L2CACHE */
/* Provide simple definitions to concentrate the inline conditional
* compilation in one place.
*/
# define l2cc_initialize() (0)
# define l2cc_enable()
# define l2cc_disable()
# define l2cc_sync()
@ -254,5 +255,5 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
# define l2cc_flush_all()
# define l2cc_flush(s,e)
#endif /* CONFIG_ARMV7A_L2CC */
#endif /* CONFIG_ARCH_L2CACHE */
#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */

4
arch/arm/src/common/up_initialize.c
View File

@ -246,5 +246,9 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
/* Initialize the L2 cache if present and selected */
up_l2ccinitialize();
board_led_on(LED_IRQSENABLED);
}

14
arch/arm/src/common/up_internal.h
View File

@ -449,6 +449,14 @@ void lowconsole_init(void);
void weak_function up_dmainitialize(void);
#endif
/* Cache control ************************************************************/
#ifdef CONFIG_ARCH_L2CACHE
void up_l2ccinitialize(void);
#else
# define up_l2ccinitialize()
#endif
/* Memory management ********************************************************/
#if CONFIG_MM_REGIONS > 1
@ -475,10 +483,10 @@ void board_led_off(int led);
/* Networking ***************************************************************/
/* Defined in board/up_network.c for board-specific ethernet implementations,
* or chip/xyx_ethernet.c for chip-specific ethernet implementations, or
/* Defined in board/up_network.c for board-specific Ethernet implementations,
* or chip/xyx_ethernet.c for chip-specific Ethernet implementations, or
* common/up_etherstub.c for a cornercase where the network is enabled yet
* there is no ethernet driver to be initialized.
* there is no Ethernet driver to be initialized.
*/
#ifdef CONFIG_NET

4
arch/arm/src/sama5/sam_boot.c
View File

@ -703,10 +703,6 @@ void up_boot(void)
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* Enable the L2 cache */
DEBUGVERIFY(l2cc_initialize());
#ifdef CONFIG_ARCH_RAMFUNCS
/* Copy any necessary code sections from FLASH to RAM. The correct
* destination in SRAM is given by _sramfuncs and _eramfuncs. The