Add SAML21 MCLK header file
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Gregory Nutt
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/************************************************************************************
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* arch/arm/src/samdl/chip/saml_mclk.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Ateml-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_MCLK_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_MCLK_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* MCLK register offsets ************************************************************/
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#define SAM_MCLK_CTRLA_OFFSET 0x0000 /* PAC write protection */
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#define SAM_MCLK_INTENCLR_OFFSET 0x0001 /* Interrupt enable clear */
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#define SAM_MCLK_INTENSET_OFFSET 0x0002 /* Interrupt enable set */
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#define SAM_MCLK_INTFLAG_OFFSET 0x0003 /* Interrupt flag status and clear */
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#define SAM_MCLK_CPUDIV_OFFSET 0x0004 /* CPU clock division */
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#define SAM_MCLK_LPDIV_OFFSET 0x0005 /* Low-power clock division */
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#define SAM_MCLK_BUPDIV_OFFSET 0x0006 /* Backup clock division */
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/* 0x0007-0x000f: Reserved */
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#define SAM_MCLK_AHBMASK_OFFSET 0x0010 /* AHB mask */
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#define SAM_MCLK_APBAMASK_OFFSET 0x0010 /* APBA mask */
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#define SAM_MCLK_APBBMASK_OFFSET 0x0010 /* APBB mask */
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#define SAM_MCLK_APBCMASK_OFFSET 0x0010 /* APBC mask */
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#define SAM_MCLK_APBDMASK_OFFSET 0x0010 /* APBD mask */
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#define SAM_MCLK_APBEMASK_OFFSET 0x0010 /* APBE mask */
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/* MCLK register addresses **********************************************************/
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#define SAM_MCLK_CTRLA (SAM_MCLK_BASE+SAM_MCLK_CTRLA_OFFSET)
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#define SAM_MCLK_INTENCLR (SAM_MCLK_BASE+SAM_MCLK_INTENCLR_OFFSET)
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#define SAM_MCLK_INTENSET (SAM_MCLK_BASE+SAM_MCLK_INTENSET_OFFSET)
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#define SAM_MCLK_INTFLAG (SAM_MCLK_BASE+SAM_MCLK_INTFLAG_OFFSET)
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#define SAM_MCLK_CPUDIV (SAM_MCLK_BASE+SAM_MCLK_CPUDIV_OFFSET)
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#define SAM_MCLK_LPDIV (SAM_MCLK_BASE+SAM_MCLK_LPDIV_OFFSET)
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#define SAM_MCLK_BUPDIV (SAM_MCLK_BASE+SAM_MCLK_BUPDIV_OFFSET)
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#define SAM_MCLK_AHBMASK (SAM_MCLK_BASE+SAM_MCLK_AHBMASK_OFFSET)
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#define SAM_MCLK_APBAMASK (SAM_MCLK_BASE+SAM_MCLK_APBAMASK_OFFSET)
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#define SAM_MCLK_APBBMASK (SAM_MCLK_BASE+SAM_MCLK_APBBMASK_OFFSET)
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#define SAM_MCLK_APBCMASK (SAM_MCLK_BASE+SAM_MCLK_APBCMASK_OFFSET)
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#define SAM_MCLK_APBDMASK (SAM_MCLK_BASE+SAM_MCLK_APBDMASK_OFFSET)
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#define SAM_MCLK_APBEMASK (SAM_MCLK_BASE+SAM_MCLK_APBEMASK_OFFSET)
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/* MCLK register bit definitions ****************************************************/
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/* PAC write protection. All bits in this register are reserved. */
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/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and
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* clear.
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*/
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#define MCLK_INT_CKRDY (1 << 0) /* Bit 0: Clock ready */
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/* CPU clock division (8-bit divider) */
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/* Low-power clock division (8-bit divider) */
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/* Backup clock division (8-bit divider) */
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/* AHB mask */
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#define MCLK_AHBMASK_APBA (1 << 0) /* Bit 0: APBA AHB clock enable */
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#define MCLK_AHBMASK_APBB (1 << 1) /* Bit 1: APBB AHB clock enable */
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#define MCLK_AHBMASK_APBC (1 << 2) /* Bit 2: APBC AHB clock enable */
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#define MCLK_AHBMASK_APBD (1 << 3) /* Bit 3: APBD AHB clock enable */
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#define MCLK_AHBMASK_APBE (1 << 4) /* Bit 4: APBE AHB clock enable */
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#define MCLK_AHBMASK_DSU (1 << 5) /* Bit 5: DSU AHB clock enable */
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#define MCLK_AHBMASK_NVMCTRL (1 << 8) /* Bit 8: NVMCTRL AHB clock enable */
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#define MCLK_AHBMASK_DMAC (1 << 11) /* Bit 11: DMAC AHB clock enable */
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#define MCLK_AHBMASK_USB (1 << 12) /* Bit 12: USB AHB clock enable */
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#define MCLK_AHBMASK_PAC (1 << 14) /* Bit 14: PAC AHB clock enable */
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/* APBA mask */
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#define MCLK_APBAMASK_PM (1 << 0) /* Bit 0: PM APBA clock enable */
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#define MCLK_APBAMASK_MCLK (1 << 1) /* Bit 1: MCLK APBA clock enable */
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#define MCLK_APBAMASK_RSTC (1 << 2) /* Bit 2: RSTC APBA clock enable */
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#define MCLK_APBAMASK_OCCTRL (1 << 3) /* Bit 3: OSCCTRL APBA clock enable */
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#define MCLK_APBAMASK_OSC32KCTRL (1 << 4) /* Bit 4: OSC32KCTRL APBA clock enable */
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#define MCLK_APBAMASK_SUPC (1 << 5) /* Bit 5: SUPC APBA clock enable */
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#define MCLK_APBAMASK_GCLK (1 << 6) /* Bit 6: GCLK APBA clock enable */
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#define MCLK_APBAMASK_WDT (1 << 7) /* Bit 7: WDT APBA clock enable */
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#define MCLK_APBAMASK_RTC (1 << 8) /* Bit 8: RTC APBA clock enable */
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#define MCLK_APBAMASK_EIC (1 << 9) /* Bit 9: EIC APBA clock enable */
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#define MCLK_APBAMASK_PORT (1 << 10) /* Bit 10: PORT APBA clock enable */
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/* APBB mask */
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#define MCLK_APBBMASK_USB (1 << 0) /* Bit 0: USB APBB clock enable */
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#define MCLK_APBBMASK_DSU (1 << 1) /* Bit 1: DSU APBB clock enable */
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#define MCLK_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL APBB clock enable */
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/* APBC mask */
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#define MCLK_APBCMASK_SERCOM0 (1 << 0) /* Bit 0: SERCOM0 APBC clock enable */
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#define MCLK_APBCMASK_SERCOM1 (1 << 1) /* Bit 1: SERCOM1 APBC clock enable */
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#define MCLK_APBCMASK_SERCOM2 (1 << 2) /* Bit 2: SERCOM2 APBC clock enable */
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#define MCLK_APBCMASK_SERCOM3 (1 << 3) /* Bit 3: SERCOM3 APBC clock enable */
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#define MCLK_APBCMASK_SERCOM4 (1 << 4) /* Bit 4: SERCOM4 APBC clock enable */
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#define MCLK_APBCMASK_TCC0 (1 << 5) /* Bit 5: TCC0 APBC clock enable */
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#define MCLK_APBCMASK_TCC1 (1 << 6) /* Bit 6: TCC1 APBC clock enable */
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#define MCLK_APBCMASK_TCC2 (1 << 7) /* Bit 7: TCC2 APBC clock enable */
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#define MCLK_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 APBC clock enable */
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#define MCLK_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 APBC clock enable */
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#define MCLK_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 APBC clock enable */
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#define MCLK_APBCMASK_TC3 (1 << 11) /* Bit 11: TC3 APBC clock enable */
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#define MCLK_APBCMASK_DAC (1 << 12) /* Bit 12: DAC APBC clock enable */
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#define MCLK_APBCMASK_AES (1 << 13) /* Bit 13: AES APBC clock enable */
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#define MCLK_APBCMASK_TRNG (1 << 14) /* Bit 14: TRNG APBC clock enable */
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/* APBD mask */
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#define MCLK_APBDMASK_EVSYS (1 << 0) /* Bit 0: EVSYS APBD clock enable */
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#define MCLK_APBDMASK_SERCOM5 (1 << 1) /* Bit 1: SERCOM5 APBD clock enable */
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#define MCLK_APBDMASK_TC4 (1 << 2) /* Bit 2: TC4 APBD clock enable */
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#define MCLK_APBDMASK_ADC (1 << 3) /* Bit 3: ADC APBD clock enable */
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#define MCLK_APBDMASK_AC (1 << 4) /* Bit 4: AC APBD clock enable */
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#define MCLK_APBDMASK_PTC (1 << 5) /* Bit 5: PTC APBD clock enable */
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#define MCLK_APBDMASK_OPAMP (1 << 6) /* Bit 6: OpAmp APBD clock enable */
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#define MCLK_APBDMASK_CCL (1 << 7) /* Bit 7: CCL APBD clock enable */
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/* APBE mask */
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#define MCLK_APBEMASK_PAC (1 << 0) /* Bit 0: PAC APBE clock enable */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_MCLK_H */
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