boards/pic32mz-starterkit: Fix building with Sourcery toolchain
Fixing an issue that occurred When building with the Sourcery CodeBench Lite MIPS Toolchain for Linux (CONFIG_MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE).
This commit is contained in:
Nathan Hartman
Xiang Xiao
parent
1b3cac19a0
commit
d383db53f9
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@ -31,6 +31,10 @@ ifeq ($(CONFIG_MIPS32_TOOLCHAIN_PINGUINOW),y)
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LDSCRIPT = pinguino-debug.ld
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endif
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ifeq ($(CONFIG_MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE),y)
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LDSCRIPT = sourcery-debug.ld
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endif
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ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y)
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LDSCRIPT = xc32-debug.ld
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MIPS_MPROCESSOR = 32MZ2048ECM144
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@ -0,0 +1,325 @@
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/****************************************************************************
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* boards/mips/pic32mz/pic32mz-starterkit/scripts/sourcery-debug.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Memory Regions ***********************************************************/
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MEMORY
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{
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/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
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* program FLASH at physical address 0x1d000000 but is always accessed
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* at KSEG0 address 0x9d00:0000
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*/
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kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
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/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
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* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
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* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
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* may be mapped to the lower boot alias region (0x1fc00000,
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* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
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* This linker script assumes that Boot Flash 1 is mapped to the lower
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* alias region and Boot Flash 2 to the upper region.
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*
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* NOTE: This linker script simply writes into the lower boot alias,
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* whichever boot FLASH that may correspond to. The other boot FLASH
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* is simply ignored.
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*
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* The initial reset vector is in KSEG1, but all other accesses are in
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* KSEG0.
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*
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* REGION PHYSICAL KSEG SIZE
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* DESCRIPTION START ADDR (BYTES)
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* ------------- ---------- ------ ----------------------
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* Exceptions:*
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* Reset 0x1fc00000 KSEG1 512 512
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* TLB Refill 0x1fc00200 KSEG1 256 768
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* Cache Error 0x1fc00300 KSEG1 128 896
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* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
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* Interrupt 0x1fc00400 KSEG1 128 1152
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* JTAG 0x1fc00480 KSEG1 16 1168
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* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
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* Debug code 0x1fc02000 KSEG1 4096-16 12272
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* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
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* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
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*
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* Exceptions assume:
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*
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* STATUS: BEV=0/1 and EXL=0
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* CAUSE: IV=1
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* JTAG: ProbEn=0
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* And multi-vector support disabled
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*/
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kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
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kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
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kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
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kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
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kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
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kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
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kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
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kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
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kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
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/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
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* of data memory at physical address 0x00000000. Since the PIC32MZ
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* has no data cache, this memory is always accessed through KSEG1.
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*
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* When used with MPLABX, we need to set aside 512 bytes of memory
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* for use by MPLABX and 128 for DSP register storage.
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*/
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kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
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}
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OUTPUT_FORMAT("elf32-tradlittlemips")
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OUTPUT_ARCH(mips)
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ENTRY(__start)
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SECTIONS
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{
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/* Boot FLASH sections */
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.reset :
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{
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KEEP (*(.reset))
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} > kseg1_reset
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/* Exception handlers. The following is assumed:
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*
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* STATUS: BEV=1 and EXL=0
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* CAUSE: IV=1
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* JTAG: ProbEn=0
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* And multi-vector support disabled
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*
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* In that configuration, the vector locations become:
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*
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* Reset, Soft Reset bfc0:0000
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* TLB Refill bfc0:0200
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* Cache Error bfc0:0300
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* All others bfc0:0380
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* Interrupt bfc0:0400
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* EJTAG Debug bfc0:0480
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*/
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/* KSEG1 exception handler "trampolines" */
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.gen_excpt :
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{
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KEEP (*(.gen_excpt))
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} > kseg1_genexcpt
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.ebase_excpt :
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{
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KEEP (*(.ebase_excpt))
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} > kseg1_ebexcpt
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.bev_excpt :
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{
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KEEP (*(.bev_excpt))
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} > kseg1_bevexcpt
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.int_excpt :
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{
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KEEP (*(.int_excpt))
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} > kseg1_intexcpt
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.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
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.start :
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{
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/* KSEG0 Reset startup logic */
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*(.start)
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/* KSEG0 exception handlers */
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*(.nmi_handler)
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*(.bev_handler)
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*(.int_handler)
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} > kseg0_bootmem
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.dbg_code = ORIGIN(kseg1_dbgcode);
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.adevcfg :
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{
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KEEP (*(.adevcfg))
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} > kseg1_adevcfg
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.devcfg :
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{
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KEEP (*(.devcfg))
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} > kseg1_devcfg
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/* Program FLASH sections */
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.text :
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{
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_stext = ABSOLUTE(.);
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*(.text .text.*)
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*(.stub)
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KEEP (*(.text.*personality*))
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*(.gnu.linkonce.t.*)
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*(.gnu.warning)
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*(.mips16.fn.*)
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*(.mips16.call.*)
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/* Read-only data is included in the text section */
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*(.rodata .rodata.*)
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*(.rodata1)
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*(.gnu.linkonce.r.*)
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/* Small initialized constant global and static data */
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*(.sdata2 .sdata2.*)
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*(.gnu.linkonce.s2.*)
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/* Uninitialized constant global and static data */
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*(.sbss2 .sbss2.*)
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*(.gnu.linkonce.sb2.*)
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_etext = ABSOLUTE(.);
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} > kseg0_progmem
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/* Initialization data begins here in progmem */
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_data_loaddr = LOADADDR(.data);
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.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
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.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
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/* RAM functions are positioned at the beginning of RAM so that
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* they can be guaranteed to satisfy the 2Kb alignment requirement.
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*/
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/* This causes failures if there are no RAM functions
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.ramfunc ALIGN(2K) :
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{
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_sramfunc = ABSOLUTE(.);
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*(.ramfunc .ramfunc.*)
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_eramfunc = ABSOLUTE(.);
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} > kseg1_datamem AT > kseg0_progmem
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_ramfunc_loadaddr = LOADADDR(.ramfunc);
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_ramfunc_sizeof = SIZEOF(.ramfunc);
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_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
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_bmxdudba_address = LENGTH(kseg1_datamem) ;
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_bmxdupba_address = LENGTH(kseg1_datamem) ;
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*/
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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KEEP (*(.gnu.linkonce.d.*personality*))
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*(.data1)
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} > kseg1_datamem AT > kseg0_progmem
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.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
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_gp = ALIGN(16) + 0x7FF0 ;
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.got :
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{
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*(.got.plt) *(.got)
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} > kseg1_datamem AT > kseg0_progmem
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.sdata :
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{
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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} > kseg1_datamem AT > kseg0_progmem
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.lit8 :
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{
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*(.lit8)
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} > kseg1_datamem AT > kseg0_progmem
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.lit4 :
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{
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*(.lit4)
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} >kseg1_datamem AT>kseg0_progmem
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.sbss :
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{
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. = ALIGN(16);
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_sbss = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon)
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} >kseg1_datamem
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.bss :
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{
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*(.dynbss)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(16);
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_ebss = ABSOLUTE(.);
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} > kseg1_datamem
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/* Stabs debugging sections */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/DISCARD/ : { *(.note.GNU-stack) }
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}
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