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armv8-m:fix log warnning 

armv8-m/arm_securefault.c:72:11: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
   72 |   sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS),
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit is contained in:
anjiahao 2023-12-19 20:00:28 +08:00 committed by Xiang Xiao
parent fecc5091af
commit ce6d308cef
3 changed files with 8 additions and 7 deletions
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2
arch/arm/src/armv8-m/arm_hardfault.c
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@ -162,7 +162,7 @@ int arm_hardfault(int irq, void *context, void *arg)
hfalert("PANIC!!! Hard Fault!:"); hfalert("PANIC!!! Hard Fault!:");
hfalert("\tIRQ: %d regs: %p\n", irq, context); hfalert("\tIRQ: %d regs: %p\n", irq, context);
hfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" hfalert("\tBASEPRI: %08" PRIx8 " PRIMASK: %08" PRIx8 " IPSR: %08"
PRIx32 " CONTROL: %08" PRIx32 "\n", PRIx32 " CONTROL: %08" PRIx32 "\n",
getbasepri(), getprimask(), getipsr(), getcontrol()); getbasepri(), getprimask(), getipsr(), getcontrol());
hfalert("\tCFSR: %08" PRIx32 " HFSR: %08" PRIx32 " DFSR: %08" hfalert("\tCFSR: %08" PRIx32 " HFSR: %08" PRIx32 " DFSR: %08"

4
arch/arm/src/armv8-m/arm_memfault.c
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@ -66,9 +66,9 @@ int arm_memfault(int irq, void *context, void *arg)
mfalert("PANIC!!! Memory Management Fault:\n"); mfalert("PANIC!!! Memory Management Fault:\n");
mfalert("\tIRQ: %d context: %p\n", irq, context); mfalert("\tIRQ: %d context: %p\n", irq, context);
mfalert("\tCFSR: %08x MMFAR: %08x\n", mfalert("\tCFSR: %08" PRIx32 " MMFAR: %08" PRIx32 "\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR)); getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
mfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" mfalert("\tBASEPRI: %08" PRIx32 " PRIMASK: %08" PRIx32 " IPSR: %08"
PRIx32 " CONTROL: %08" PRIx32 "\n", PRIx32 " CONTROL: %08" PRIx32 "\n",
getbasepri(), getprimask(), getipsr(), getcontrol()); getbasepri(), getprimask(), getipsr(), getcontrol());

9
arch/arm/src/armv8-m/arm_securefault.c
View File

@ -66,12 +66,13 @@ int arm_securefault(int irq, void *context, void *arg)
sfalert("PANIC!!! Secure Fault:\n"); sfalert("PANIC!!! Secure Fault:\n");
sfalert("\tIRQ: %d regs: %p\n", irq, context); sfalert("\tIRQ: %d regs: %p\n", irq, context);
sfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" sfalert("\tBASEPRI: %08" PRIx8 " PRIMASK: %08" PRIx8 " IPSR: %08"
PRIx32 " CONTROL: %08" PRIx32 "\n", PRIx32 " CONTROL: %08" PRIx32 "\n",
getbasepri(), getprimask(), getipsr(), getcontrol()); getbasepri(), getprimask(), getipsr(), getcontrol());
sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS), sfalert("\tCFSR: %08" PRIx32 " HFSR: %08" PRIx32 " DFSR: %08" PRIx32 "\n",
getreg32(NVIC_HFAULTS), getreg32(NVIC_DFAULTS)); getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
sfalert("\tBFAR: %08x AFSR: %08x SFAR: %08x\n", getreg32(NVIC_DFAULTS));
sfalert("\tBFAR: %08" PRIx32 " AFSR: %08" PRIx32 " SFAR: %08" PRIx32 "\n",
getreg32(NVIC_BFAULT_ADDR), getreg32(NVIC_AFAULTS), getreg32(NVIC_BFAULT_ADDR), getreg32(NVIC_AFAULTS),
getreg32(SAU_SFAR)); getreg32(SAU_SFAR));