From ce6d308cefdef44468e29145e8d529b78cc9297b Mon Sep 17 00:00:00 2001 From: anjiahao Date: Tue, 19 Dec 2023 20:00:28 +0800 Subject: [PATCH] armv8-m:fix log warnning armv8-m/arm_securefault.c:72:11: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=] 72 | sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS), | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: anjiahao --- arch/arm/src/armv8-m/arm_hardfault.c | 2 +- arch/arm/src/armv8-m/arm_memfault.c | 4 ++-- arch/arm/src/armv8-m/arm_securefault.c | 9 +++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/armv8-m/arm_hardfault.c b/arch/arm/src/armv8-m/arm_hardfault.c index 83c9e3d5ed..d69c4f599c 100644 --- a/arch/arm/src/armv8-m/arm_hardfault.c +++ b/arch/arm/src/armv8-m/arm_hardfault.c @@ -162,7 +162,7 @@ int arm_hardfault(int irq, void *context, void *arg) hfalert("PANIC!!! Hard Fault!:"); hfalert("\tIRQ: %d regs: %p\n", irq, context); - hfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" + hfalert("\tBASEPRI: %08" PRIx8 " PRIMASK: %08" PRIx8 " IPSR: %08" PRIx32 " CONTROL: %08" PRIx32 "\n", getbasepri(), getprimask(), getipsr(), getcontrol()); hfalert("\tCFSR: %08" PRIx32 " HFSR: %08" PRIx32 " DFSR: %08" diff --git a/arch/arm/src/armv8-m/arm_memfault.c b/arch/arm/src/armv8-m/arm_memfault.c index e9bdbc580e..685e2657bd 100644 --- a/arch/arm/src/armv8-m/arm_memfault.c +++ b/arch/arm/src/armv8-m/arm_memfault.c @@ -66,9 +66,9 @@ int arm_memfault(int irq, void *context, void *arg) mfalert("PANIC!!! Memory Management Fault:\n"); mfalert("\tIRQ: %d context: %p\n", irq, context); - mfalert("\tCFSR: %08x MMFAR: %08x\n", + mfalert("\tCFSR: %08" PRIx32 " MMFAR: %08" PRIx32 "\n", getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR)); - mfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" + mfalert("\tBASEPRI: %08" PRIx32 " PRIMASK: %08" PRIx32 " IPSR: %08" PRIx32 " CONTROL: %08" PRIx32 "\n", getbasepri(), getprimask(), getipsr(), getcontrol()); diff --git a/arch/arm/src/armv8-m/arm_securefault.c b/arch/arm/src/armv8-m/arm_securefault.c index fb0f2a4736..82285196eb 100644 --- a/arch/arm/src/armv8-m/arm_securefault.c +++ b/arch/arm/src/armv8-m/arm_securefault.c @@ -66,12 +66,13 @@ int arm_securefault(int irq, void *context, void *arg) sfalert("PANIC!!! Secure Fault:\n"); sfalert("\tIRQ: %d regs: %p\n", irq, context); - sfalert("\tBASEPRI: %08x PRIMASK: %08x IPSR: %08" + sfalert("\tBASEPRI: %08" PRIx8 " PRIMASK: %08" PRIx8 " IPSR: %08" PRIx32 " CONTROL: %08" PRIx32 "\n", getbasepri(), getprimask(), getipsr(), getcontrol()); - sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS), - getreg32(NVIC_HFAULTS), getreg32(NVIC_DFAULTS)); - sfalert("\tBFAR: %08x AFSR: %08x SFAR: %08x\n", + sfalert("\tCFSR: %08" PRIx32 " HFSR: %08" PRIx32 " DFSR: %08" PRIx32 "\n", + getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS), + getreg32(NVIC_DFAULTS)); + sfalert("\tBFAR: %08" PRIx32 " AFSR: %08" PRIx32 " SFAR: %08" PRIx32 "\n", getreg32(NVIC_BFAULT_ADDR), getreg32(NVIC_AFAULTS), getreg32(SAU_SFAR));