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Extend STM32 Ethernet operating frequency to 180MHz: 

-Extend frequency range options to 180 MHz for STM32 ETH_MACMIIA_CR
-Fix a typo in a frequency range option in LPC43
-Only configure the PPS GPIO if the PTP protocol is enabled

From Sebastien Lorquet
This commit is contained in:
Sebastien Lorquet 2015-07-17 07:44:12 -06:00 committed by Gregory Nutt
parent 652371c919
commit cc1b108d71
3 changed files with 6 additions and 4 deletions
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2
arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
View File

@ -209,7 +209,7 @@
# define ETH_MACMIIA_CR_20_35 (2 << ETH_MACMIIA_CR_SHIFT) /* 20-35 MHz CLK_M4_ETHERNET/16 */
# define ETH_MACMIIA_CR_35_60 (3 << ETH_MACMIIA_CR_SHIFT) /* 35-60 MHz CLK_M4_ETHERNET/26 */
# define ETH_MACMIIA_CR_150_168 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-168 MHz CLK_M4_ETHERNET/102 */
# define ETH_MACMIIA_CR_150_168 (5 << ETH_MACMIIA_CR_SHIFT) /* 250 - 300 MHz CLK_M4_ETHERNET/124 */
# define ETH_MACMIIA_CR_250_300 (5 << ETH_MACMIIA_CR_SHIFT) /* 250-300 MHz CLK_M4_ETHERNET/124 */
# define ETH_MACMIIA_CR_DIV42 (8 << ETH_MACMIIA_CR_SHIFT) /* 60-100 MHz CLK_M4_ETHERNET/42 */
# define ETH_MACMIIA_CR_DIV62 (9 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
# define ETH_MACMIIA_CR_DIV16 (10 << ETH_MACMIIA_CR_SHIFT) /* 20-35 MHz CLK_M4_ETHERNET/16 */

2
arch/arm/src/stm32/chip/stm32_eth.h
View File

@ -261,7 +261,7 @@
# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */
# define ETH_MACMIIAR_CR_150_180 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-180 MHz HCLK/102 */
#endif
#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)

6
arch/arm/src/stm32/stm32_eth.c
View File

@ -255,8 +255,8 @@
# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_60_100
#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000
# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_100_150
#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 168000000
# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_168
#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 180000000
# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_180
#else
# error "STM32_HCLK_FREQUENCY not supportable"
#endif
@ -3662,9 +3662,11 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
#endif
#endif
#ifdef CONFIG_STM32_ETH_PTP
/* Enable pulse-per-second (PPS) output signal */
stm32_configgpio(GPIO_ETH_PPS_OUT);
#endif
}
/****************************************************************************