From cc08ae67cb5adf3da444f100466c70a6c89f8f44 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= <michal.lyszczek@bofc.pl>
Date: Wed, 3 Aug 2022 12:24:26 +0200
Subject: [PATCH] stm32wl5_pwr: add support to boot second CPU (cortex-m0)
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Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
 arch/arm/src/stm32wl5/stm32wl5_pwr.c | 15 +++++++++++++++
 arch/arm/src/stm32wl5/stm32wl5_pwr.h | 11 +++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c
index 059a9ca24f..58ec08cb17 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c
+++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c
@@ -29,6 +29,7 @@
 #include <stdbool.h>
 #include <errno.h>
 
+#include "hardware/stm32wl5_pwr.h"
 #include "arm_internal.h"
 #include "stm32wl5_pwr.h"
 #include "stm32wl5_rcc.h"
@@ -106,3 +107,17 @@ bool stm32wl5_pwr_enablebkp(bool writable)
 
   return waswritable;
 }
+
+/****************************************************************************
+ * Name: stm32wl5_pwr_boot_c2
+ *
+ * Description:
+ *   Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby
+ *   modes.
+ *
+ ****************************************************************************/
+
+void stm32wl5_pwr_boot_c2(void)
+{
+  modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT);
+}
diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/stm32wl5_pwr.h
index 55ec2b3403..5cfb6e4519 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_pwr.h
+++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.h
@@ -68,6 +68,17 @@ extern "C"
 
 bool stm32wl5_pwr_enablebkp(bool writable);
 
+/****************************************************************************
+ * Name: stm32wl5_pwr_boot_c2
+ *
+ * Description:
+ *   Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby
+ *   modes.
+ *
+ ****************************************************************************/
+
+void stm32wl5_pwr_boot_c2(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }