From c4b3672937319a5cfac037287be17ec26674f8c0 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Wed, 19 Jan 2022 13:06:55 +0200 Subject: [PATCH] RISC-V MMU driver: fix region setting for L1/L2 page tables The region setting worked for L3 (Sv39) entries only. This fixes the procedure so that L1 (Gigapages) or L2 (Megapages) can be also set with it. --- arch/risc-v/src/common/riscv_mmu.c | 16 +++++++++++++--- arch/risc-v/src/common/riscv_mmu.h | 5 ++++- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/common/riscv_mmu.c b/arch/risc-v/src/common/riscv_mmu.c index d2d88ed18e..d0e18c2b5c 100644 --- a/arch/risc-v/src/common/riscv_mmu.c +++ b/arch/risc-v/src/common/riscv_mmu.c @@ -43,6 +43,13 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_ARCH_MMU_TYPE_SV39 +static const size_t g_pgt_sizes[] = +{ + RV_MMU_L1_PAGE_SIZE, RV_MMU_L2_PAGE_SIZE, RV_MMU_L3_PAGE_SIZE +}; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -53,7 +60,7 @@ void mmu_ln_setentry(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr, uintptr_t *lntable = (uintptr_t *)lnvaddr; uint32_t index; - DEBUGASSERT(ptlevel <= RV_MMU_PT_LEVELS); + DEBUGASSERT(ptlevel > 0 && ptlevel <= RV_MMU_PT_LEVELS); /* Test if this is a leaf PTE, if it is, set A+D even if they are not used * by the implementation. @@ -97,11 +104,14 @@ void mmu_ln_map_region(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr, uintptr_t vaddr, size_t size, uint32_t mmuflags) { uintptr_t end_paddr = paddr + size; + size_t page_size = g_pgt_sizes[ptlevel - 1]; + + DEBUGASSERT(ptlevel > 0 && ptlevel <= RV_MMU_PT_LEVELS); while (paddr < end_paddr) { mmu_ln_setentry(ptlevel, lnvaddr, paddr, vaddr, mmuflags); - paddr += RV_MMU_PAGE_SIZE; - vaddr += RV_MMU_PAGE_SIZE; + paddr += page_size; + vaddr += page_size; } } diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h index 492d7bf4fc..18fd96244e 100644 --- a/arch/risc-v/src/common/riscv_mmu.h +++ b/arch/risc-v/src/common/riscv_mmu.h @@ -88,7 +88,10 @@ #define RV_MMU_PT_LEVELS (3) #define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \ (RV_MMU_PT_LEVELS - (_n))) -#define RV_MMU_SATP_MODE SATP_MODE_SV39 +#define RV_MMU_SATP_MODE (SATP_MODE_SV39) +#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */ +#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */ +#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */ #else #error "Unsupported RISC-V MMU implementation selected" #endif /* CONFIG_ARCH_MMU_TYPE_SV39 */