Added options for I-Cache & D-Cache, in STM32F2 & STM32F4.
This commit is contained in:
Fotis Panagiotopoulos
Mateusz Szafoni
parent
151a9253f4
commit
c101076704
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@ -1399,6 +1399,8 @@ config STM32_STM32F20XX
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bool
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default n
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select ARCH_CORTEXM3
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select STM32_HAVE_FLASH_ICACHE
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select STM32_HAVE_FLASH_DCACHE
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select STM32_HAVE_CRYP
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select STM32_HAVE_OTGFS
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select STM32_HAVE_OTGHS
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@ -1549,6 +1551,8 @@ config STM32_STM32F4XXX
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default n
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select ARCH_CORTEXM4
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select ARCH_HAVE_FPU
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select STM32_HAVE_FLASH_ICACHE
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select STM32_HAVE_FLASH_DCACHE
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select STM32_HAVE_CRYP
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select STM32_HAVE_SPI2
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select STM32_HAVE_I2C2
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@ -1992,6 +1996,14 @@ menu "STM32 Peripheral Support"
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# These "hidden" settings determine whether a peripheral option is available
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# for the selected MCU
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config STM32_HAVE_FLASH_ICACHE
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bool
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default n
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config STM32_HAVE_FLASH_DCACHE
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bool
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default n
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config STM32_HAVE_OVERDRIVE
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bool
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default n
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@ -3344,25 +3356,39 @@ endchoice
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endmenu
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config STM32_FLASH_ICACHE
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bool "Enable FLASH Instruction Cache"
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default y
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depends on STM32_HAVE_ICACHE
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---help---
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Enable the FLASH instruction cache.
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config STM32_FLASH_DCACHE
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bool "Enable FLASH Data Cache"
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default y
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depends on STM32_HAVE_DCACHE
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---help---
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Enable the FLASH data cache.
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config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
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bool "Workaround for FLASH data cache corruption"
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default n
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depends on (STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE
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---help---
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Enable the workaround to fix flash data cache corruption when reading
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from one flash bank while writing on other flash bank. See your STM32
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errata to check if your STM32 is affected by this problem.
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config STM32_FLASH_PREFETCH
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bool "Enable FLASH Pre-fetch"
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default y if STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
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default n
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depends on STM32_STM32F20XX || STM32_STM32F4XXX
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---help---
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Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
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Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled
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on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
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properly and enabling this option may interfere with ADC accuracy.
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config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
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bool "Workaround for FLASH data cache corruption"
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default n
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depends on STM32_STM32F20XX || STM32_STM32F4XXX
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---help---
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Enable the workaround to fix flash data cache corruption when reading
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from one flash bank while writing on other flash bank. See your STM32
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errata to check if your STM32 is affected by this problem.
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choice
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prompt "JTAG Configuration"
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default STM32_JTAG_DISABLE
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@ -182,7 +182,8 @@ static inline void rcc_enableahb1(void)
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#ifdef CONFIG_STM32_ETHMAC
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/* Ethernet MAC clocking */
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regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN);
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regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN |
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RCC_AHB1ENR_ETHMACRXEN);
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#ifdef CONFIG_STM32_ETH_PTP
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/* Precision Time Protocol (PTP) */
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@ -644,13 +645,21 @@ static void stm32_stdclockconfig(void)
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
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/* Enable FLASH prefetch, instruction cache, data cache,
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* and 5 wait states.
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*/
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
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#else
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
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regval = (FLASH_ACR_LATENCY_5
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#ifdef CONFIG_STM32_FLASH_ICACHE
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| FLASH_ACR_ICEN
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#endif
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#ifdef CONFIG_STM32_FLASH_DCACHE
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| FLASH_ACR_DCEN
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#endif
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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| FLASH_ACR_PRFTEN
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#endif
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);
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putreg32(regval, STM32_FLASH_ACR);
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/* Select the main PLL as system clock source */
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@ -662,7 +671,8 @@ static void stm32_stdclockconfig(void)
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/* Wait until the PLL source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_PLL);
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#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK)
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/* Low speed internal clock source LSI */
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@ -781,7 +781,13 @@ static void stm32_stdclockconfig(void)
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* and 5 wait states.
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*/
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN
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regval = (FLASH_ACR_LATENCY_5
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#ifdef CONFIG_STM32_FLASH_ICACHE
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| FLASH_ACR_ICEN
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#endif
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#ifdef CONFIG_STM32_FLASH_DCACHE
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| FLASH_ACR_DCEN
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#endif
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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| FLASH_ACR_PRFTEN
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#endif
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