arch/risc-v: implement sbi_ipi_send

And SBI ipi support.

Fixup: 4f63ca1418 ("arch/risc-v: unfiy IPI access)
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>

arch/risc-v/src/common/riscv_internal.h

@@ -171,6 +171,7 @@
 /* SBI Extension IDs */
 
 #define SBI_EXT_HSM             0x48534D
+#define SBI_EXT_IPI             0x735049
 #define SBI_EXT_TIME            0x54494D45
 
 /* SBI function IDs for TIME extension */
@@ -181,6 +182,10 @@
 
 #define SBI_EXT_HSM_HART_START  0x0
 
+/* SBI function IDs for IPI extension */
+
+#define SBI_EXT_IPI_SEND_IPI  0x0
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -325,6 +330,7 @@ static inline void riscv_set_basestack(uintptr_t base, uintptr_t size)
 /* RISC-V SBI wrappers ******************************************************/
 
 #ifdef CONFIG_ARCH_USE_S_MODE
+uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase);
 void riscv_sbi_set_timer(uint64_t stime_value);
 uint64_t riscv_sbi_get_time(void);
 uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr,

arch/risc-v/src/common/riscv_ipi.h

@@ -34,10 +34,12 @@
 
 static inline void riscv_ipi_send(int cpu)
 {
-#if defined(RISCV_IPI)
+#if defined(CONFIG_ARCH_USE_S_MODE)
+  riscv_sbi_send_ipi(0x1, cpu);
+#elif defined(RISCV_IPI)
   putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
 #else
-  PANIC();
+#  error "No IPI support for this SoC"
 #endif
 }
 

arch/risc-v/src/common/supervisor/riscv_sbi.c

@@ -125,6 +125,12 @@ uint64_t riscv_sbi_get_time(void)
 #endif
 }
 
+uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase)
+{
+  return sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,
+      hmask, hbase, 0, 0, 0, 0);
+}
+
 #ifndef CONFIG_NUTTSBI
 uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr,
                                    uintptr_t a1)

arch/risc-v/src/k230/hardware/k230_clint.h

@@ -44,4 +44,6 @@
 #  define K230_TIMECMP       K230_CLINT_MTIMECMP
 #endif
 
+#define RISCV_IPI            K230_IPI
+
 #endif /* __ARCH_RISCV_SRC_K230_HARDWARE_K230_CLINT_H */

arch/risc-v/src/nuttsbi/CMakeLists.txt

@@ -24,6 +24,8 @@ if(CONFIG_NUTTSBI)
 
   list(APPEND SRCS sbi_mtimer.c sbi_mexception.c sbi_mcall.c sbi_mscratch.c)
 
+  list(APPEND SRCS sbi_ipi.c)
+
   target_sources(arch PRIVATE ${SRCS})
 
 endif()

arch/risc-v/src/nuttsbi/Kconfig

@@ -15,6 +15,12 @@ config NUTTSBI_HART_CNT
 	int "Amount of harts in SoC"
 	default 1
 
+config NUTTSBI_IPI_BASE
+	hex "MSWI base address"
+	default 0
+	---help---
+		Sets the address of mtimecmp memory mapped register
+
 config NUTTSBI_MTIME_BASE
 	hex "MTIME base address"
 	default 0

arch/risc-v/src/nuttsbi/Make.defs

@@ -24,7 +24,7 @@ ifeq ($(CONFIG_NUTTSBI),y)
 
 SBI_ASRCS += sbi_mtrap.S sbi_vectors.S sbi_head.S
 SBI_CSRCS += sbi_mscratch.c sbi_mcall.c sbi_start.c
-SBI_CSRCS += sbi_mexception.c sbi_mtimer.c
+SBI_CSRCS += sbi_mexception.c sbi_mtimer.c sbi_ipi.c
 
 INCLUDES  += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)nuttsbi
 

arch/risc-v/src/nuttsbi/sbi_internal.h

@@ -43,7 +43,15 @@
 
 #define MMODE_IRQSTACK      (1024)
 
-/* Timer interrupt is the only one we handle, others are discarded */
+/* IPI memory mapped registers */
+
+#define IPI_IRQ             (3)
+
+/* IPI memory mapped registers */
+
+#define IPI_BASE            (CONFIG_NUTTSBI_IPI_BASE)
+
+/* Timer interrupt */
 
 #define MTIMER_IRQ          (7)
 
@@ -97,6 +105,20 @@ void sbi_mscratch_assign(uintptr_t hartid);
 
 void sbi_start(void) noreturn_function;
 
+/****************************************************************************
+ * Name: sbi_send_ipi
+ *
+ * Description:
+ *   Send an inter-processor interrupt to all the harts defined
+ *
+ * Input Parameters:
+ *   hmask - Mask fo CPU to send IPI
+ *   hbase - The firset CPU id to send
+ *
+ ****************************************************************************/
+
+void sbi_send_ipi(uintptr_t hmask, uintptr_t hbase);
+
 /****************************************************************************
  * Name: sbi_init_mtimer
  *

arch/risc-v/src/nuttsbi/sbi_ipi.c

@@ -0,0 +1,56 @@
+/****************************************************************************
+ * arch/risc-v/src/nuttsbi/sbi_ipi.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <nuttx/irq.h>
+
+#include <arch/barriers.h>
+
+#include <stdint.h>
+
+#include "riscv_internal.h"
+
+#include "sbi_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void sbi_send_ipi(uintptr_t hmask, uintptr_t hbase)
+{
+  uintptr_t i;
+
+  for (i = hbase; hmask; i++, hmask >>= 1)
+    {
+      if (hmask & 1)
+        {
+          putreg32(1, IPI_BASE + 4 * i);
+        }
+    }
+}

arch/risc-v/src/nuttsbi/sbi_mcall.c

@@ -53,6 +53,9 @@ void sbi_mcall_handle(uintptr_t *regs)
 
   switch (regs[REG_A7])
   {
+    case SBI_EXT_IPI:
+      sbi_send_ipi(regs[REG_A0], regs[REG_A1]);
+      break;
     case SBI_EXT_TIME:
       switch (regs[REG_A6])
       {

arch/risc-v/src/nuttsbi/sbi_mtrap.S

@@ -70,10 +70,19 @@ machine_trap:
 
   sll        a0, a0, 1            /* Shift msbit out */
   li         a1, MTIMER_IRQ * 2   /* Machine timer irq ? (shifted left) */
+  beq        a0, a1, 2f
+  li         a1, IPI_IRQ * 2      /* Machine IPI irq ? (shifted left) */
   bne        a0, a1, 1f
 
   /* Delegate interrupt to S-mode handler */
 
+  li         a0, MIP_MSIP
+  csrc       CSR_MIE, a0
+  li         a0, MIP_SSIP
+  csrs       CSR_MIP, a0
+  j          1f
+
+2:
   li         a0, MIP_MTIP
   csrc       CSR_MIE, a0
   li         a0, MIP_STIP

boards/risc-v/k230/canmv230/configs/master/defconfig

@@ -78,6 +78,7 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_PROMPT_STRING=""
 CONFIG_NSH_READLINE=y
 CONFIG_NUTTSBI=y
+CONFIG_NUTTSBI_IPI_BASE=0xf04000000
 CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000
 CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8
 CONFIG_PATH_INITIAL="/system/bin"

boards/risc-v/k230/canmv230/configs/nsbi/defconfig

@@ -71,6 +71,7 @@ CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_READLINE=y
 CONFIG_NUTTSBI=y
+CONFIG_NUTTSBI_IPI_BASE=0xf04000000
 CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000
 CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8
 CONFIG_PATH_INITIAL="/system/bin"

boards/risc-v/k230/canmv230/configs/remote/defconfig

@@ -64,6 +64,7 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_PROMPT_STRING="remote> "
 CONFIG_NSH_READLINE=y
 CONFIG_NUTTSBI=y
+CONFIG_NUTTSBI_IPI_BASE=0xf04000000
 CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000
 CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8
 CONFIG_PATH_INITIAL="/system/bin"

boards/risc-v/mpfs/icicle/configs/knsh/defconfig

@@ -78,6 +78,7 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_LINELEN=160
 CONFIG_NSH_STRERROR=y
 CONFIG_NUTTSBI=y
+CONFIG_NUTTSBI_IPI_BASE=0x02000000
 CONFIG_NUTTSBI_MTIMECMP_BASE=0x02004000
 CONFIG_NUTTSBI_MTIME_BASE=0x0200bff8
 CONFIG_PREALLOC_TIMERS=4