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boards/arm/stm32l4/nucleo-l432kc/: Remove LPTIM1/2 duplicated entrys on Timer Configuration Menu. Timers TIM3, TIM4, TIM5, TIM8 and TIM17 are not available on STM32L432KC. Added support for timers LPTIM1/2.

This commit is contained in:
Daniel P. Carvalho 2020-01-09 15:22:48 -06:00 committed by Gregory Nutt
parent 51eaed8765
commit bac282ecbf
4 changed files with 72 additions and 109 deletions
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26
arch/arm/src/stm32l4/Kconfig
View File

@ -2993,19 +2993,6 @@ endif # !STM32L4_PWM_MULTICHAN
endif # STM32L4_TIM17_PWM
config STM32L4_LPTIM1_PWM
bool "LPTIM1 PWM"
default n
depends on STM32L4_LPTIM1
select PWM
---help---
Reserve Low-power timer 1 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32L4_LPTIM1
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
if STM32L4_LPTIM1_PWM
if STM32L4_PWM_MULTICHAN
@ -3049,19 +3036,6 @@ endif # !STM32L4_PWM_MULTICHAN
endif # STM32L4_LPTIM1_PWM
config STM32L4_LPTIM2_PWM
bool "LPTIM2 PWM"
default n
depends on STM32L4_LPTIM2
select PWM
---help---
Reserve Low-power timer 2 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32L4_LPTIM2
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
if STM32L4_LPTIM2_PWM
if STM32L4_PWM_MULTICHAN

16
boards/arm/stm32l4/nucleo-l432kc/include/board.h
View File

@ -246,6 +246,22 @@
#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
/* LPTIM2 PWM output
* REVISIT : Add support for the other clock sources, LSE, LSI and HSI
*
* CH1 | 1(A4) 2(A8)
*/
#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1)
# define STM32L4_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN
#endif
#if 1
# define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_1
#else
# define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_2
#endif
/*******************************************************************************
* Public Data
******************************************************************************/

69
boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h
View File

@ -62,16 +62,21 @@
/* Clocking *****************************************************************/
#if defined(HSI_CLOCK_CONFIG)
/* The NUCLEOL432KC supports both HSE and LSE crystals (X2 and X3). However, as
* shipped, the X3 crystal is not populated. Therefore the Nucleo-L432KC
* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
/* The NUCLEOL432KC supports both HSE and LSE crystals (X2 and X3).
* However, asshipped, the X3 crystal is not populated. Therefore the
* Nucleo-L432KC will need to run off the 16MHz HSI clock, or the 32khz-
* synced MSI.
*
* System Clock source : PLL (HSI)
* SYSCLK(Hz) : 80000000 Determined by PLL configuration
* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz)
* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz)
* SYSCLK(Hz) : 80000000 Determined by PLL configuration
* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE)
* (Max 80 MHz)
* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE)
* (Max 80 MHz)
* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1)
* (Max 80 MHz)
* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2)
* (Max 80 MHz)
* HSI Frequency(Hz) : 16000000 (nominal)
* PLLM : 1 (STM32L4_PLLCFG_PLLM)
* PLLN : 10 (STM32L4_PLLCFG_PLLN)
@ -109,11 +114,17 @@
*
* Formulae:
*
* VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8
* VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz
* PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable
* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable
* PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable
* VCO input frequency = PLL input clock frequency / PLLM,
* 1 <= PLLM <= 8
* VCO output frequency = VCO input frequency × PLLN,
* 8 <= PLLN <= 86, frequency range 64 to
* 344 MHz
* PLL output P (SAI3) clock frequency = VCO frequency / PLLP,
* PLLP = 7, or 17, or 0 to disable
* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ,
* PLLQ = 2, 4, 6, or 8, or 0 to disable
* PLL output R (CLK) clock frequency = VCO frequency / PLLR,
* PLLR = 2, 4, 6, or 8, or 0 to disable
*
* PLL output P is used for SAI
* PLL output Q is used for OTG FS, SDMMC, RNG
@ -150,10 +161,15 @@
* The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined
*
* SAI1VCO input frequency = PLL input clock frequency
* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable
* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable
* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable
* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N,
* 8 <= PLLSAI1N <= 86, frequency range
* 64 to 344 MHz
* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P,
* PLLP = 7, or 17, or 0 to disable
* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q,
* PLLQ = 2, 4, 6, or 8, or 0 to disable
* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R,
* PLLR = 2, 4, 6, or 8, or 0 to disable
*
* We will configure like this
*
@ -168,9 +184,13 @@
* The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined
*
* SAI2VCO input frequency = PLL input clock frequency
* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable
* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable
* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N,
* 8 <= PLLSAI1N <= 86, frequency range
* 64 to 344 MHz
* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P,
* PLLP = 7, or 17, or 0 to disable
* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R,
* PLLR = 2, 4, 6, or 8, or 0 to disable
*
* We will configure like this
*
@ -178,11 +198,14 @@
*
* ----------------------------------------
*
* TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime.
* TODO: The STM32L is a low power peripheral and all these clocks should be
* configurable at runtime.
*
* ----------------------------------------
*
* TODO These clock sources can be configured in Kconfig (this is not a board feature)
* TODO These clock sources can be configured in Kconfig (this is not a
* board feature)
*
* USART1
* USART2
* USART3
@ -286,6 +309,8 @@
#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (80MHz) */

70
boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c
View File

@ -61,6 +61,7 @@
******************************************************************************/
/* Configuration **************************************************************/
/* PWM
*
* The nucleo-l432kc has no real on-board PWM devices, but the board can be
@ -137,8 +138,8 @@ int stm32l4_pwm_setup(void)
}
#endif
#if defined(CONFIG_STM32L4_TIM3_PWM)
pwm = stm32l4_pwminitialize(3);
#if defined(CONFIG_STM32L4_TIM15_PWM)
pwm = stm32l4_pwminitialize(15);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
@ -155,8 +156,8 @@ int stm32l4_pwm_setup(void)
}
#endif
#if defined(CONFIG_STM32L4_TIM4_PWM)
pwm = stm32l4_pwminitialize(4);
#if defined(CONFIG_STM32L4_TIM16_PWM)
pwm = stm32l4_pwminitialize(16);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
@ -173,8 +174,8 @@ int stm32l4_pwm_setup(void)
}
#endif
#if defined(CONFIG_STM32L4_TIM5_PWM)
pwm = stm32l4_pwminitialize(5);
#if defined(CONFIG_STM32L4_LPTIM1_PWM)
pwm = stm32l4_lp_pwminitialize(1);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
@ -191,8 +192,8 @@ int stm32l4_pwm_setup(void)
}
#endif
#if defined(CONFIG_STM32L4_TIM8_PWM)
pwm = stm32l4_pwminitialize(8);
#if defined(CONFIG_STM32L4_LPTIM2_PWM)
pwm = stm32l4_lp_pwminitialize(2);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
@ -209,59 +210,6 @@ int stm32l4_pwm_setup(void)
}
#endif
#if defined(CONFIG_STM32L4_TIM15_PWM)
pwm = stm32l4_pwminitialize(15);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
return -ENODEV;
}
/* Register the PWM driver at "/dev/pwm6" */
ret = pwm_register("/dev/pwm6", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_STM32L4_TIM16_PWM)
pwm = stm32l4_pwminitialize(16);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
return -ENODEV;
}
/* Register the PWM driver at "/dev/pwm7" */
ret = pwm_register("/dev/pwm7", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_STM32L4_TIM17_PWM)
pwm = stm32l4_pwminitialize(17);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
return -ENODEV;
}
/* Register the PWM driver at "/dev/pwm8" */
ret = pwm_register("/dev/pwm8", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
/* Now we are initialized */
initialized = true;