Add ethernet interrupt handler
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3106 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
d6fc1a3825
commit
ba88a8aa88
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@ -160,14 +160,14 @@
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/* EMAC statistics (debug only) */
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#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
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struct ez80mac_statistics_s
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struct lm3s_statistics_s
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{
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uint32_t rx_int; /* Number of Rx interrupts received */
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uint32_t rx_packets; /* Number of packets received (sum of the following): */
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uint32_t rx_ip; /* Number of Rx IP packets received */
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uint32_t rx_arp; /* Number of Rx ARP packets received */
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uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */
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uint32_t rx_pktsize; /* Number of dropped, too small or too bigr */
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uint32_t rx_pktsize; /* Number of dropped, too small or too big */
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uint32_t rx_errors; /* Number of Rx errors (reception error) */
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uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */
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uint32_t tx_int; /* Number of Tx interrupts received */
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@ -200,7 +200,7 @@ struct lm3s_driver_s
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WDOG_ID ld_txtimeout; /* TX timeout timer */
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#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
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struct ez80mac_statistics_s ld_stat;
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struct lm3s_statistics_s ld_stat;
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#endif
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/* This holds the information visible to uIP/NuttX */
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@ -289,6 +289,36 @@
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* Private Types
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****************************************************************************/
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/* EMAC statistics (debug only) */
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#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
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struct lpc17_statistics_s
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{
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#if ENABLE_WOL
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uint32_t wol; /* Wake-up interrupts */
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#endif
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uint32_t rx_finished; /* Rx finished interrupts */
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uint32_t rx_done; /* Rx done interrupts */
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uint32_t rx_ovrerrors; /* Number of Rx overrun error interrupts */
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uint32_t rx_errors; /* Number of Rx error interrupts (OR of other errors) */
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uint32_t rx_packets; /* Number of packets received (sum of the following): */
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uint32_t rx_ip; /* Number of Rx IP packets received */
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uint32_t rx_arp; /* Number of Rx ARP packets received */
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uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */
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uint32_t rx_pktsize; /* Number of dropped, too small or too big */
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uint32_t tx_packets; /* Number of Tx packets queued */
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uint32_t tx_finished; /* Tx finished interrupts */
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uint32_t tx_done; /* Tx done interrupts */
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uint32_t tx_underrun; /* Number of Tx underrun error interrupts */
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uint32_t tx_errors; /* Number of Tx error inerrupts (OR of other errors) */
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uint32_t tx_timeouts; /* Number of Tx timeout errors */
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};
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# define EMAC_STAT(priv,name) priv->lp_stat.name++
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#else
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# define EMAC_STAT(priv,name)
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#endif
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/* The lpc17_driver_s encapsulates all state information for a single hardware
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* interface
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*/
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@ -311,6 +341,10 @@ struct lpc17_driver_s
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#endif
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WDOG_ID lp_txpoll; /* TX poll timer */
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WDOG_ID lp_txtimeout; /* TX timeout timer */
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#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
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struct lpc17_statistics_s lp_stat;
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#endif
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/* This holds the information visible to uIP/NuttX */
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@ -742,24 +776,86 @@ static void lpc17_txdone(FAR struct lpc17_driver_s *priv)
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static int lpc17_interrupt(int irq, FAR void *context)
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{
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register FAR struct lpc17_driver_s *priv = &g_ethdrvr[0];
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uint32_t status;
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/* Disable Ethernet interrupts */
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/* Get the interrupt status (zero means no interrupts pending). */
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/* Get and clear interrupt status bits */
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status = lpc17_getreg(LPC17_ETH_INTST);
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if (status != 0)
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{
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/* Handle each pending interrupt */
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/* Check for receive errors */
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/* Handle interrupts according to status bit settings */
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if ((status & ETH_INT_RXOVR) != 0)
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{
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lpc17_putreg(ETH_INT_RXOVR, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, rx_ovrerrors);
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}
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/* Check if we received an incoming packet, if so, call lpc17_receive() */
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if ((status & ETH_INT_RXERR) != 0)
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{
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lpc17_putreg(ETH_INT_RXERR, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, rx_errors);
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}
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lpc17_receive(priv);
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/* Check if we received an incoming packet, if so, call lpc17_receive() */
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/* Check is a packet transmission just completed. If so, call lpc17_txdone */
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if ((status & ETH_INT_RXFIN) != 0)
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{
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lpc17_putreg(ETH_INT_RXFIN, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, rx_finished);
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DEBUGASSERT(lpc17_getreg(LPC17_ETH_RXPRODIDX) == lpc17_getreg(LPC17_ETH_RXCONSIDX));
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}
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lpc17_txdone(priv);
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if ((status & ETH_INT_RXDONE) != 0)
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{
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lpc17_putreg(ETH_INT_RXDONE, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, rx_done);
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lpc17_receive(priv);
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}
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/* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if
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* there are no pending transmissions.
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*/
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/* Check for Tx errors */
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if ((status & ETH_INT_TXUNR) != 0)
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{
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lpc17_putreg(ETH_INT_TXUNR, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, tx_underrun);
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}
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if ((status & ETH_INT_TXERR) != 0)
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{
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lpc17_putreg(ETH_INT_TXERR, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, tx_errors);
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}
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/* Check is a packet transmission just completed. If so, call lpc17_txdone */
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if ((status & ETH_INT_TXFIN) != 0)
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{
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lpc17_putreg(ETH_INT_TXFIN, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, tx_finished);
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}
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if ((status & ETH_INT_TXDONE) != 0)
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{
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lpc17_putreg(ETH_INT_TXDONE, LPC17_ETH_INTCLR);
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EMAC_STAT(priv, tx_done);
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lpc17_txdone(priv);
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}
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/* Check for Wake-Up on Lan */
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#if CONFIG_NET_WOL
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if ((status & ETH_INT_WKUP) != 0)
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{
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lpc17_putreg(ETH_INT_WKUP, LPC17_ETH_INTCLR);
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INTCLEAR = EMAC_INT_WOL;
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EMAC_STAT(priv, wol);
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# warning "Missing logic"
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}
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#endif
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}
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return OK;
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}
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@ -857,7 +953,7 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
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/* Reset the Ethernet controller (again) */
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@ -954,7 +1050,7 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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lpc17_putreg((ETH_INT_RXOVR | ETH_INT_RXERR | ETH_INT_RXFIN | ETH_INT_RXDONE |
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ETH_INT_TXUNR | ETH_INT_TXERR | ETH_INT_TXFIN | ETH_INT_TXDONE),
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LPC17_ETH_INTEN);
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LPC17_ETH_INTEN);
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#endif
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/* Set and activate a timer process */
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@ -1620,7 +1716,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv)
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{
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*txdesc++ = pktaddr;
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*txdesc++ = (TXDESC_CONTROL_INT | (LPC17_MAXPACKET_SIZE - 1));
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pktaddr += LPC17_MAXPACKET_SIZE;
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pktaddr += LPC17_MAXPACKET_SIZE;
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}
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/* Initialize Tx status */
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@ -459,7 +459,7 @@
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#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */
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/* Bits 6-11: Reserved */
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#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */
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#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect math WoL interrupt */
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#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect match WoL interrupt */
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/* Bits 14-31: Reserved */
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/* Receive filter WoL status register (RXFLWOLST) AND
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* Receive filter WoL clear register (RXFLWOLCLR)
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