From b47839b9c2649174df39f66e0669e897a4ed8f4e Mon Sep 17 00:00:00 2001
From: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Date: Tue, 10 Sep 2024 08:58:27 +0200
Subject: [PATCH] arch/intel64: fix IRQ conflict with GOLDFISH

Also move MSI IRQ definition to place where other IRQ definitions are.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
---
 arch/x86_64/include/intel64/irq.h     | 14 +++++++++++---
 arch/x86_64/src/intel64/intel64_irq.c |  1 -
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/x86_64/include/intel64/irq.h b/arch/x86_64/include/intel64/irq.h
index fbcdf54500..78ebfa4135 100644
--- a/arch/x86_64/include/intel64/irq.h
+++ b/arch/x86_64/include/intel64/irq.h
@@ -346,10 +346,18 @@
 #define HPET0_IRQ    IRQ2
 #define HPET1_IRQ    IRQ8
 
-/* Use IRQ15 IRQ16 for SMP */
+/* NuttX custom interrupts configuration starts from here.
+ * IRQ16-IRQ23 are reserved for GOLDFISH so we start from IRQ24.
+ */
 
-#define SMP_IPI_IRQ  IRQ15
-#define SMP_IPI_ASYNC_IRQ  IRQ16
+/* Use IRQ24 IRQ25 for SMP */
+
+#define SMP_IPI_IRQ        IRQ24
+#define SMP_IPI_ASYNC_IRQ  IRQ25
+
+/* Use IRQ32 and above for MSI */
+
+#define IRQ_MSI_START      IRQ32
 
 /* Common register save structure created by up_saveusercontext() and by
  * ISR/IRQ interrupt processing.
diff --git a/arch/x86_64/src/intel64/intel64_irq.c b/arch/x86_64/src/intel64/intel64_irq.c
index aae0f6f0c7..38f44a480f 100644
--- a/arch/x86_64/src/intel64/intel64_irq.c
+++ b/arch/x86_64/src/intel64/intel64_irq.c
@@ -48,7 +48,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define IRQ_MSI_START        IRQ32
 #define X86_64_MAR_DEST      0xfee00000
 #define X86_64_MDR_TYPE      0x4000