From b28f87e3f0cd4ec901b2a716fea15378cb4cfd09 Mon Sep 17 00:00:00 2001 From: chao an Date: Fri, 25 Oct 2024 11:36:52 +0800 Subject: [PATCH] arm/gicv3: replace this_cpu() to up_cpu_index() If the core id needs to be included in the hardware register calculation, up_cpu_index() should be used instead of this_cpu(). Signed-off-by: chao an --- arch/arm/src/armv8-r/arm_gicv3.c | 5 +++-- arch/arm64/include/irq.h | 4 ++++ arch/arm64/src/common/arm64_gicv3.c | 5 +++-- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/armv8-r/arm_gicv3.c b/arch/arm/src/armv8-r/arm_gicv3.c index d5e9b75759..1cd20ee972 100644 --- a/arch/arm/src/armv8-r/arm_gicv3.c +++ b/arch/arm/src/armv8-r/arm_gicv3.c @@ -250,7 +250,7 @@ void arm_gic_irq_enable(unsigned int intid) if (GIC_IS_SPI(intid)) { - arm_gic_write_irouter(this_cpu(), intid); + arm_gic_write_irouter(up_cpu_index(), intid); } putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx)); @@ -809,7 +809,8 @@ static void arm_gic_init(void) int err; cpu = this_cpu(); - g_gic_rdists[cpu] = CONFIG_GICR_BASE + cpu * CONFIG_GICR_OFFSET; + g_gic_rdists[cpu] = CONFIG_GICR_BASE + + up_cpu_index() * CONFIG_GICR_OFFSET; err = gic_validate_redist_version(); if (err) diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h index aad83b14e9..820be30c7f 100644 --- a/arch/arm64/include/irq.h +++ b/arch/arm64/include/irq.h @@ -383,6 +383,10 @@ static inline void up_irq_restore(irqstate_t flags) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_MULTICPU +# ifndef MPID_TO_CORE +# define MPID_TO_CORE(mpid) \ + (((mpid) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +# endif # define up_cpu_index() ((int)MPID_TO_CORE(GET_MPIDR())) #endif /* CONFIG_ARCH_HAVE_MULTICPU */ diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c index 3e52e17bfe..74b2859966 100644 --- a/arch/arm64/src/common/arm64_gicv3.c +++ b/arch/arm64/src/common/arm64_gicv3.c @@ -257,7 +257,7 @@ void arm64_gic_irq_enable(unsigned int intid) #ifndef CONFIG_ARM64_GICV3_SPI_ROUTING_CPU0 if (GIC_IS_SPI(intid)) { - arm64_gic_write_irouter((GET_MPIDR() & MPIDR_ID_MASK), intid); + arm64_gic_write_irouter(up_cpu_index(), intid); } #endif @@ -952,7 +952,8 @@ static void arm64_gic_init(void) int err; cpu = this_cpu(); - g_gic_rdists[cpu] = CONFIG_GICR_BASE + cpu * CONFIG_GICR_OFFSET; + g_gic_rdists[cpu] = CONFIG_GICR_BASE + + up_cpu_index() * CONFIG_GICR_OFFSET; err = gic_validate_redist_version(); if (err)