OrgApache/incubator-nuttx
OrgApache
/
incubator-nuttx
mirror of https://github.com/apache/incubator-nuttx.git
1
0
Fork 0
Code Issues Releases Wiki Activity

I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S. 

The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor.  But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's.  It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition)

So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.
This commit is contained in:
Manohara HK 2017-02-13 06:33:15 -06:00 committed by Gregory Nutt
parent c433724b23
commit b154531838
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/src/armv7-r/cp15_coherent_dcache.S
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/cp15_coherent_dcache.S
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
@ -93,7 +93,7 @@
.type cp15_coherent_dcache, function
cp15_coherent_dcache:
mrc CP15_CTR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
@ -111,7 +111,7 @@ cp15_coherent_dcache:
dsb
mrc CP15_CTR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
and r3, r3, #0xf /* Isolate the IminLine field */
mov r2, #4
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
@ -127,8 +127,10 @@ cp15_coherent_dcache:
blo 1b
mov r0, #0
#ifdef CONFIG_SMP
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */
#endif
mcr CP15_BPIALL(r0) /* Invalidate all branch predictors */
dsb
isb