arch/risc-v: Refine riscv_initialstate.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
26370cd2f7
commit
b11e90f384
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/rv64gc/riscv_initialstate.c
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* arch/risc-v/src/common/riscv_initialstate.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -55,7 +55,7 @@
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void up_initial_state(struct tcb_s *tcb)
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{
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struct xcptcontext *xcp = &tcb->xcp;
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uint64_t regval;
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uintptr_t regval;
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/* Initialize the idle thread stack */
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@ -93,6 +93,13 @@ void up_initial_state(struct tcb_s *tcb)
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xcp->regs[REG_EPC] = (uintptr_t)tcb->start;
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/* Setup thread local storage pointer */
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#ifdef CONFIG_SCHED_THREAD_LOCAL
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xcp->regs[REG_TP] = (uintptr_t)tcb->stack_alloc_ptr +
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sizeof(struct tls_info_s);
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#endif
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/* Set the initial value of the interrupt context register.
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*
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* Since various RISC-V platforms use different interrupt
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@ -1,132 +0,0 @@
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/****************************************************************************
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* arch/risc-v/src/rv32im/riscv_initialstate.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <string.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "riscv_internal.h"
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#include "riscv_arch.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_initial_state
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*
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* Description:
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* A new thread is being started and a new TCB
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* has been created. This function is called to initialize
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* the processor specific portions of the new TCB.
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*
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* This function must setup the initial architecture registers
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* and/or stack so that execution will begin at tcb->start
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* on the next context switch.
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*
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****************************************************************************/
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void up_initial_state(struct tcb_s *tcb)
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{
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struct xcptcontext *xcp = &tcb->xcp;
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uint32_t regval;
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/* Initialize the idle thread stack */
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if (tcb->pid == 0)
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{
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tcb->stack_alloc_ptr = (void *)(g_idle_topstack -
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CONFIG_IDLETHREAD_STACKSIZE);
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tcb->stack_base_ptr = tcb->stack_alloc_ptr;
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tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
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#ifdef CONFIG_STACK_COLORATION
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/* If stack debug is enabled, then fill the stack with a
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* recognizable value that we can use later to test for high
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* water marks.
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*/
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riscv_stack_color(tcb->stack_alloc_ptr, 0);
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#endif /* CONFIG_STACK_COLORATION */
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}
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/* Initialize the initial exception register context structure */
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memset(xcp, 0, sizeof(struct xcptcontext));
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/* Save the initial stack pointer. Hmmm.. the stack is set to the very
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* beginning of the stack region. Some functions may want to store data on
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* the caller's stack and it might be good to reserve some space. However,
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* only the start function would do that and we have control over that one
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*/
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xcp->regs[REG_SP] = (uint32_t)tcb->stack_base_ptr +
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tcb->adj_stack_size;
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/* Save the task entry point */
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xcp->regs[REG_EPC] = (uint32_t)tcb->start;
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/* Setup thread local storage pointer */
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#ifdef CONFIG_SCHED_THREAD_LOCAL
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xcp->regs[REG_TP] = (uint32_t)tcb->stack_alloc_ptr +
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sizeof(struct tls_info_s);
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#endif
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/* If this task is running PIC, then set the PIC base register to the
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* address of the allocated D-Space region.
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*/
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#ifdef CONFIG_PIC
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# warning "Missing logic"
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#endif
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/* Set privileged- or unprivileged-mode, depending on how NuttX is
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* configured and what kind of thread is being started.
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*
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* If the kernel build is not selected, then all threads run in
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* privileged thread mode.
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*/
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#ifdef CONFIG_BUILD_KERNEL
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# warning "Missing logic"
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#endif
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/* Set the initial value of the interrupt context register.
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*
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* Since various RISC-V platforms use different interrupt
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* methodologies, the value of the interrupt context is
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* part specific.
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*
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*/
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regval = riscv_get_newintctx();
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xcp->regs[REG_INT_CTX] = regval;
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}
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