SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however

This commit is contained in:
Gregory Nutt 2013-07-28 15:07:35 -06:00
parent 63eb68bc0a
commit afdd9a7416
9 changed files with 183 additions and 29 deletions

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@ -318,7 +318,7 @@ Writing to FLASH using SAM-BA
1. Exit the terminal emulation program and remove the USB cable from
the DBGU port (J14)
2. Connect the USB cable to the device USB port (J20)
3. JP9 must open so that (BMS == 1) to boot from on-chip Boot ROM
3. JP9 must open (BMS == 1) to boot from on-chip Boot ROM.
4. Press and maintain PB4 CS_BOOT button and power up the board. PB4
CS_BOOT button prevents booting from Nand or serial Flash by
disabling Flash Chip Selects after having powered the board, you can
@ -332,7 +332,9 @@ Writing to FLASH using SAM-BA
9. When you are finished writing to FLASH, remove the USB cable from J20
and re-connect the serial link on USB CDC / DBGU connector (J14) and
re-open the terminal emulator program.
10. Power cycle the board.
10. If you loaded code in NOR flash (CS0), then you will need to close
JP9 (BMS == 0) to force booting out of NOR flash (see NOTE).
11. Power cycle the board.
NOTES: By closing JP9 (BMS == 0), you can force the board to boot
directly to NOR FLASH. Executing from other memories will require that
@ -688,12 +690,15 @@ Configurations
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
3. This configuration executes out of internal SRAM an can only
3. This configuration executes out of internal SRAM and can only
be loaded via JTAG.
CONFIG_SAMA5_BOOT_ISRAM=y : Boot into internal SRAM
CONFIG_BOOT_RUNFROMISRAM=y : Run from internal SRAM
STATUS:
2013-7-28: This configuration was verified functional.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
@ -714,16 +719,17 @@ Configurations
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
3. This configuration executes out of internal SRAM an can only
be loaded via JTAG.
3. This configuration executes out of CS0 NOR flash and can only
be loaded via JTAG. 128MB
CONFIG_SAMA5_BOOT_ISRAM=y : Boot into internal SRAM
CONFIG_BOOT_RUNFROMISRAM=y : Run from internal SRAM
CONFIG_SAMA5_BOOT_CS0FLASH=y : Boot from FLASH on CS0
CONFIG_BOOT_RUNFROMFLASH=y : Run in place on FLASH (vs copying to RAM)
CONFIG_SAMA5_EBICS0=y : Enable CS0 external memory
CONFIG_SAMA5_EBICS0_SIZE=134217728 : Memory size is 128KB
CONFIG_SAMA5_EBICS0_NOR=y : Memory type is NOR FLASH
NOTE: In order to boot in this configuration, you need to close the
BMS jumper.
STATUS:
2013-7-26: This ostest configuration is too large to fit in SAMA5
internal SRAM (along with a usable heap and a 16KB page table).
I do not want to simplify this test because I will, eventually,
need to do the entire OS test. But I will need to configure this
to run out of FLASH or SDRAM in this future. For now, I created
the smaller 'hello' configuration for the basic bringup.

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@ -44,7 +44,7 @@ ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y)
LDSCRIPT = ddram.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
# LDSCRIPT = cs0flash.ld
LDSCRIPT = norflash.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y)
# LDSCRIPT = cs1flash.ld

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@ -217,6 +217,15 @@
#define BUTTON_USER1_BIT (1 << BUTTON_USER1)
/************************************************************************************
* Assembly Language Macros
************************************************************************************/
#ifdef __ASSEMBLY__
.macro config_sdram
.endm
#endif /* __ASSEMBLY__ */
/************************************************************************************
* Public Data
************************************************************************************/
@ -309,5 +318,5 @@ xcpt_t up_irqbutton(int id, xcpt_t irqhandler);
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* !__ASSEMBLY__ */
#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_H */

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@ -44,7 +44,7 @@ ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y)
LDSCRIPT = ddram.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
# LDSCRIPT = cs0flash.ld
LDSCRIPT = norflash.ld
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y)
# LDSCRIPT = cs1flash.ld

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@ -168,15 +168,26 @@ CONFIG_SAMA5_USART1=y
# External Memory Configuration
#
# CONFIG_SAMA5_DDRCS is not set
# CONFIG_SAMA5_EBICS0 is not set
CONFIG_SAMA5_EBICS0=y
CONFIG_SAMA5_EBICS0_SIZE=134217728
# CONFIG_SAMA5_EBICS0_SRAM is not set
# CONFIG_SAMA5_EBICS0_PSRAM is not set
# CONFIG_SAMA5_EBICS0_PROM is not set
# CONFIG_SAMA5_EBICS0_EEPROM is not set
# CONFIG_SAMA5_EBICS0_EPROM is not set
# CONFIG_SAMA5_EBICS0_LCD is not set
CONFIG_SAMA5_EBICS0_NOR=y
# CONFIG_SAMA5_EBICS0_NAND is not set
# CONFIG_SAMA5_EBICS1 is not set
# CONFIG_SAMA5_EBICS2 is not set
# CONFIG_SAMA5_EBICS3 is not set
CONFIG_SAMA5_BOOT_ISRAM=y
# CONFIG_SAMA5_BOOT_ISRAM is not set
CONFIG_SAMA5_BOOT_CS0FLASH=y
#
# Heap Configuration
#
CONFIG_SAMA5_ISRAM_HEAP=y
#
# Architecture Options
@ -199,9 +210,6 @@ CONFIG_ARCH_STACKDUMP=y
#
CONFIG_BOARD_LOOPSPERMSEC=16717
# CONFIG_ARCH_CALIBRATION is not set
CONFIG_RAM_START=0x00300000
CONFIG_RAM_VSTART=0x00300000
CONFIG_RAM_SIZE=114688
CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
CONFIG_ARCH_INTERRUPTSTACK=0
@ -209,11 +217,21 @@ CONFIG_ARCH_INTERRUPTSTACK=0
# Boot options
#
# CONFIG_BOOT_RUNFROMEXTSRAM is not set
# CONFIG_BOOT_RUNFROMFLASH is not set
CONFIG_BOOT_RUNFROMISRAM=y
CONFIG_BOOT_RUNFROMFLASH=y
# CONFIG_BOOT_RUNFROMISRAM is not set
# CONFIG_BOOT_RUNFROMSDRAM is not set
# CONFIG_BOOT_COPYTORAM is not set
#
# Boot Memory Configuration
#
CONFIG_RAM_START=0x00304000
CONFIG_RAM_VSTART=0x00304000
CONFIG_RAM_SIZE=114688
CONFIG_FLASH_START=0x1000000
CONFIG_FLASH_VSTART=0x1000000
CONFIG_FLASH_SIZE=134217728
#
# Board Selection
#

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@ -91,8 +91,6 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)

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@ -88,8 +88,6 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)

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@ -0,0 +1,127 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/norflash.ld
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The SAMA5D3x-EK has 128MB of NOR flash at CS0 (0x1000:0000). In this
* configuration, the .text and a copy of the .data section will be loaded
* into NOR flash. NuttX .data, .bss, the IDLE stack, and the primary
* heap will be allocated in SRAM. The SAMA5D3 has 128 KB of ISRAM beginning
* at virtual address 0x0030:0000.
*
* Vectors in low memory are assumed to reside at the beginning of NOR flash
* 16KB of ISRAM is reserved at the beginning of ISRAM for the page table.
*/
MEMORY
{
norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M
isram (WRX!) : ORIGIN = 0x00304000, LENGTH = 128K - 16K
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(entry)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
*(.ARM.extab*)
*(.gnu.linkonce.armextab.*)
_etext = ABSOLUTE(.);
} > norflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > norflash
.ARM.extab : {
*(.ARM.extab*)
} > norflash
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > norflash
PROVIDE_HIDDEN (__exidx_end = .);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > isram AT > norflash
_eronly = LOADADDR(.data);
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > isram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

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@ -110,8 +110,6 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
_eronly = ABSOLUTE(.);
.paged : {
_spaged = ABSOLUTE(.);
*(.text .text.*)