drivers/clk: Change CLK_SET_RATE_NO_REPARENT to CLK_MUX_SET_RATE_NO_REPARENT
since only mux clk use this flag Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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@ -96,7 +96,7 @@ clk_mux_determine_rate(FAR struct clk_s *clk, uint32_t rate,
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uint32_t parent_rate;
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uint32_t parent_rate;
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uint32_t best = 0;
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uint32_t best = 0;
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if (clk->flags & CLK_SET_RATE_NO_REPARENT)
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if (mux->flags & CLK_MUX_SET_RATE_NO_REPARENT)
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{
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{
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parent = clk->parent;
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parent = clk->parent;
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if (clk->flags & CLK_SET_RATE_PARENT)
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if (clk->flags & CLK_SET_RATE_PARENT)
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@ -40,7 +40,6 @@
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#define CLK_SET_RATE_GATE 0x01
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#define CLK_SET_RATE_GATE 0x01
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#define CLK_SET_PARENT_GATE 0x02
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#define CLK_SET_PARENT_GATE 0x02
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#define CLK_SET_RATE_PARENT 0x04
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#define CLK_SET_RATE_PARENT 0x04
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#define CLK_SET_RATE_NO_REPARENT 0x08
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#define CLK_GET_RATE_NOCACHE 0x10
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#define CLK_GET_RATE_NOCACHE 0x10
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#define CLK_NAME_IS_STATIC 0x20
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#define CLK_NAME_IS_STATIC 0x20
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#define CLK_PARENT_NAME_IS_STATIC 0x40
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#define CLK_PARENT_NAME_IS_STATIC 0x40
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@ -71,6 +70,7 @@
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#define CLK_MUX_HIWORD_MASK 0x01
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#define CLK_MUX_HIWORD_MASK 0x01
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#define CLK_MUX_READ_ONLY 0x02
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#define CLK_MUX_READ_ONLY 0x02
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#define CLK_MUX_ROUND_CLOSEST 0x04
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#define CLK_MUX_ROUND_CLOSEST 0x04
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#define CLK_MUX_SET_RATE_NO_REPARENT 0x08
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#define CLK_PHASE_HIWORD_MASK 0x01
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#define CLK_PHASE_HIWORD_MASK 0x01
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